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/freebsd-13.1/contrib/llvm-project/lldb/source/Plugins/Trace/intel-pt/
H A DIntelPTDecoder.cpp109 std::vector<IntelPTInstruction> instructions; in DecodeInstructions() local
117 instructions.emplace_back(make_error<IntelPTError>(errcode)); in DecodeInstructions()
145 instructions.emplace_back( in DecodeInstructions()
147 instructions.emplace_back(insn); in DecodeInstructions()
153 instructions.emplace_back(insn); in DecodeInstructions()
155 instructions.emplace_back(insn, time); in DecodeInstructions()
160 return instructions; in DecodeInstructions()
209 return instructions; in DecodeInMemoryTrace()
256 if (Expected<std::vector<IntelPTInstruction>> instructions = in DoDecode() local
272 if (Expected<std::vector<IntelPTInstruction>> instructions = in DoDecode() local
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPC.td59 "Enable 64-bit instructions">;
65 "Enable floating-point instructions">;
77 "Enable SPE instructions",
143 "Enable VSX instructions",
159 "Enable Power8 direct move instructions",
256 "32Byte load and store instructions",
259 "Enable MMA instructions",
268 "Add privileged instructions">;
427 // The key column are the non-record-form instructions.
440 // The key column are the record-form instructions.
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H A DPPCScheduleP9.td15 // The maximum number of instructions to be issued at the same time.
16 // While a value of 8 is technically correct since 8 instructions can be
17 // fetched from the instruction cache. However, only 6 instructions may be
23 // There are two instructions (lxvl, lxvll) that have a latency of 6 cycles.
25 // of instructions are 4 or 5 cycles.
32 // A dispatch group is 6 instructions.
43 // Do not support SPE (Signal Processing Engine), prefixed instructions on
44 // Power 9, paired vector mem ops, MMA, PC relative mem ops, or instructions
73 // Execution (EXEC) for most other instructions.
194 // receive new instructions each cycle.
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/freebsd-13.1/contrib/subversion/subversion/libsvn_fs_x/
H A Dreps.c175 apr_array_header_t *instructions; member
207 const instruction_t *instructions; member
400 result->instructions = apr_array_make(result_pool, 0, in svn_fs_x__reps_builder_create()
582 + builder->instructions->nelts * 2 in svn_fs_x__reps_estimate_size()
751 for (i = 0; i < builder->instructions->nelts; ++i) in svn_fs_x__write_reps_container()
778 instruction_t *instructions; in svn_fs_x__read_reps_container() local
821 instructions in svn_fs_x__read_reps_container()
824 reps->instructions = instructions; in svn_fs_x__read_reps_container()
828 instruction_t *instruction = instructions + i; in svn_fs_x__read_reps_container()
871 + reps->instruction_count * sizeof(*reps->instructions) in svn_fs_x__serialize_reps_container()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagon.td31 "Hexagon ZReg extension instructions">;
34 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;
36 "Hexagon::ArchEnum::V60", "Hexagon HVX instructions",
39 "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
42 "Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
45 "Hexagon::ArchEnum::V66", "Hexagon HVX instructions",
49 "Hexagon::ArchEnum::V67", "Hexagon HVX instructions",
62 "Hexagon Audio extension instructions">;
65 "Use compound instructions">;
75 "Use memop instructions">;
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H A DHexagonInstrFormats.td9 // Addressing modes for load/store instructions
64 // instructions to not match without killing the whole decode process. It is
75 // Solo instructions, i.e., those that cannot be in a packet with others.
78 // Packed only with A or X-type instructions.
81 // Restricts slot 1 to ALU-only instructions.
85 // Predicated instructions.
135 // Addressing mode for load/store instructions.
139 // Memory access size for mem access instructions (load/store)
182 string isBrTaken = !if(isTaken, "true", "false"); // Set to "true"/"false" for jump instructions
286 // instructions to not match without killing the whole decode process. It is
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARM.td144 " etc) instructions">;
339 /// Disable +1 predication cost for instructions updating CPSR.
352 // "normal" call instructions to callees which do not return.
359 // instructions.
391 "instructions">;
429 "Enable support for BFloat16 instructions", [FeatureNEON]>;
476 "v5TExp instructions",
480 "Support ARM v6 instructions",
544 "Support ARM v8-1M Mainline instructions",
556 "Support CDE instructions",
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86.td67 "Enable SSE instructions">;
69 "Enable SSE2 instructions",
72 "Enable SSE3 instructions",
377 // rotate instructions.
400 // instructions) with conditional branches.
422 "Prefer 128-bit AVX instructions">;
426 "Prefer 256-bit AVX instructions">;
475 "instructions into a POP+LFENCE+JMP sequence.">;
493 // Direct Move instructions.
510 "normal vector instructions with shuffles">;
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H A DX86InstrFormats.td288 // Attributes specific to X86 instructions...
490 // SI - SSE 1 & 2 scalar instructions
538 // PI - SSE 1 & 2 packed instructions
578 // SSI - SSE1 instructions with XS prefix.
579 // PSI - SSE1 instructions with PS prefix.
609 // SDI - SSE2 instructions with XD prefix.
674 // S3SI - SSE3 instructions with XS prefix.
675 // S3DI - SSE3 instructions with XD prefix.
981 // MMXI - MMX instructions with TB prefix.
987 // MMXID - MMX instructions with XD prefix.
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H A DX86InstrTDX.td9 // This file describes the instructions that make up the Intel TDX instruction
15 // TDX instructions
17 // 64-bit only instructions
33 // common instructions
H A DX86InstrAMX.td9 // This file describes the instructions that make up the Intel AMX instruction
15 // AMX instructions
68 // Pseudo instructions, using immediates instead of tile registers.
69 // To be translated to the actual instructions in X86ISelLowering.cpp
130 // Pseudo instructions, using immediates instead of tile registers.
131 // To be translated to the actual instructions in X86ISelLowering.cpp
171 // Pseudo instructions, using immediates instead of tile registers.
172 // To be translated to the actual instructions in X86ISelLowering.cpp
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedPredExynos.td16 // Check the shift in arithmetic and logic instructions.
32 // Identify arithmetic instructions without or with limited extension or shift.
60 // Identify logic instructions with limited shift.
76 // Identify more logic instructions with limited shift.
111 // Identify FP instructions.
117 // Identify 128-bit NEON instructions.
120 // Identify instructions that reset a register efficiently.
148 // Identify cheap arithmetic and logic immediate instructions.
H A DAArch64.td26 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
56 "Enable ARMv8 CRC-32 checksum instructions">;
65 "Enable out of line atomics to support LSE instructions">;
91 "Enable FP16 FML instructions", [FeatureFullFP16]>;
133 "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>;
136 "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>;
142 "Enable bit permutation SVE2 instructions", [FeatureSVE2]>;
187 "Use custom handling of cheap instructions">;
191 "Use Exynos specific handling of cheap instructions",
271 "Enable v8.3-A JavaScript FP conversion instructions",
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H A DAArch64SchedPredicates.td16 // Check the extension type in arithmetic instructions.
28 // Check for shifting in extended arithmetic instructions.
55 // Check for shifting in arithmetic and logic instructions.
203 // Identify arithmetic instructions with extend.
209 // Identify arithmetic immediate instructions.
213 // Identify arithmetic instructions with shift.
217 // Identify arithmetic instructions without shift.
221 // Identify logic immediate instructions.
226 // Identify logic instructions with shift.
234 // Identify logic instructions without shift.
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H A DAArch64SchedExynosM3.td193 // Branch instructions.
203 // Move instructions.
224 // Load instructions.
230 // Store instructions.
236 // FP data instructions.
490 // Branch instructions
505 // Move instructions.
514 // Load instructions.
527 // Store instructions.
604 // ASIMD instructions.
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H A DAArch64SchedExynosM5.td539 // Branch instructions.
549 // Move instructions.
565 // Load instructions.
570 // Store instructions.
623 // Branch instructions
649 // Move instructions.
654 // Shift instructions.
668 // Load instructions.
681 // Store instructions.
774 // ASIMD instructions.
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrFormats.td27 // When there are multiple instructions that map to the same encoding (in
32 // Normal instructions. Default instantiation of a WebAssemblyInst.
48 // instructions are used for ISel and all MI passes. The stack versions of the
49 // instructions do not have register operands (they implicitly operate on the
50 // stack), and local.gets and local.sets are explicit. The register instructions
51 // are converted to their corresponding stack instructions before lowering to
54 // there is always an equivalent pair of instructions.
64 // For instructions that have no register ops, so both sets are the same.
/freebsd-13.1/usr.bin/bc/
H A Dbc.y100 static struct tree *instructions = NULL; variable
776 free(instructions);
779 instructions = p;
790 instructions[current].u.cstr = str; in cs()
801 if (instructions[current].u.astr == NULL) in as()
816 instructions[current++].index = arg; in node()
821 instructions[current++].index = arg; in node()
834 if (instructions[i].index >= 0) { in emit()
836 instructions[i].index != i) { in emit()
841 fputs(instructions[i].u.cstr, stdout); in emit()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPU.td57 "Most fp64 instructions are full rate"
290 "Additional instructions for CI+"
296 "Additional instructions for GFX8+"
344 "Has i16/f16 instructions"
350 "Has VOP3P packed instructions"
356 "Has v_movrel*_b32 instructions"
435 "Support packed fp32 instructions"
471 "Has BVH ray tracing instructions"
543 "Has mAI instructions"
611 "Has ds_*_src2 instructions"
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H A DSISchedule.td30 // Normal 16 or 32 bit VALU instructions
34 // F16 or F32 transcendental instructions (these are quarter rate)
36 // Other quarter rate VALU instructions
51 // instructions
54 // Half rate 64-bit instructions.
60 // mAI multipass instructions.
67 // FIXME: Should there be a class for instructions which are VALU
68 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
69 // instructions)
73 // MicroOpBufferSize = 1 means that instructions will always be added
/freebsd-13.1/contrib/subversion/subversion/libsvn_delta/
H A Dsvndiff.c167 svn_stringbuf_t *instructions; in encode_window() local
174 instructions = svn_stringbuf_create_empty(pool); in encode_window()
205 SVN_ERR(svn__compress_lz4(instructions->data, instructions->len, in encode_window()
207 instructions = compressed_instructions; in encode_window()
213 SVN_ERR(svn__compress_zlib(instructions->data, instructions->len, in encode_window()
215 instructions = compressed_instructions; in encode_window()
217 append_encoded_int(header, instructions->len); in encode_window()
241 *instructions_p = instructions; in encode_window()
255 svn_stringbuf_t *instructions; in window_handler() local
291 if (instructions->len > 0) in window_handler()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrFormats.td44 // A class for pseudo instructions.
45 // Pseudo instructions are not real AVR instructions. The DAG stores
46 // pseudo instructions which are replaced by real AVR instructions by
51 // the instruction is then replaced by two add instructions - one for each byte.
218 // Special format for the LPM/ELPM instructions
283 // Special encoding for the FMUL family of instructions.
310 // Arithmetic word instructions (ADIW / SBIW): <|1001|011f|kkdd|kkkk|>
442 // Conditional Branching instructions: <|1111|0fkk|kkkk|ksss|>
459 // Special, opcode only instructions: <|opcode|>
475 // Branching instructions with immediate12: <|110f|kkkk|kkkk|kkkk|>
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMSA.txt7 (semantically equivalent) instructions to be used in place of the requested
14 example, two instructions might be equally valid for some given IR and one is
31 instructions will be selected instead of vshf.[bhwd]. Unlike the ilv*,
32 and pck* instructions, this is matched from MipsISD::VSHF instead of
68 In future, the compiler may choose between these three instructions
71 between the instructions and the vselect node in one place:
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrFormats.td39 // Except for shift instructions, `H' determines whether the constant
59 // If and only if the `F' bit is 1, RI instructions modify the
70 // For arithmetic instructions (`add', `addc', `sub', `subb') `V' is
73 // otherwise. For other RI instructions, `V' is cleared.
76 // For arithmetic instructions, `C' is set/cleared if there is/is_not
133 // are reserved for instructions that may be defined in the future.
135 // If the `F' bit is 1, RR instructions modify the condition bits, `Z'
137 // the result. All RR instructions modify the `Z', `N', and `V' flags.
492 // instructions. *Note RM:: and *Note RRM::.
526 // Special instructions (popc, leadz, trailz)
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/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/
H A DInstIterator.h133 inline inst_range instructions(Function *F) { in instructions() function
142 inline const_inst_range instructions(const Function *F) { in instructions() function
147 inline inst_range instructions(Function &F) { in instructions() function
156 inline const_inst_range instructions(const Function &F) { in instructions() function

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