Searched refs:hasVGPRs (Results 1 – 4 of 4) sorted by relevance
155 return !hasVGPRs(RC) && !hasAGPRs(RC); in isSGPRClass()167 return hasAGPRs(RC) && !hasVGPRs(RC); in isAGPRClass()171 bool hasVGPRs(const TargetRegisterClass *RC) const;178 return hasVGPRs(RC) || hasAGPRs(RC); in hasVectorRegisters()
2157 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const { in hasVGPRs() function in SIRegisterInfo2324 return RC && hasVGPRs(RC); in isVGPR()2535 if (hasVGPRs(&RC)) in isProperlyAlignedRC()
896 Opcode = (RI.hasVGPRs(SrcRC)) ? in copyPhysReg()898 } else if (RI.hasVGPRs(RC) && RI.hasAGPRs(SrcRC)) { in copyPhysReg()900 } else if ((Size % 64 == 0) && RI.hasVGPRs(RC) && in copyPhysReg()1846 if (RI.hasVGPRs(EltRC)) { in expandPostRAPseudo()2562 return RI.hasVGPRs(RC) && NumInsts <= 6; in canInsertSelect()3860 const bool IsVGPR = RI.hasVGPRs(RC); in verifyInstruction()3907 if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) { in verifyInstruction()5522 if (RI.hasVGPRs(DstRC)) { in legalizeOperands()6944 if (RI.hasVGPRs(NewDstRC) || NewDstRC == &AMDGPU::VReg_1RegClass) in getDestEquivalentVGPRClass()
1173 !TRI->hasVGPRs(TRI->getRegClass(Desc.OpInfo[I].RegClass))) in legalizeScalarOperands()