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Searched refs:hasMVEIntegerOps (Results 1 – 13 of 13) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp106 if (ST->hasMVEIntegerOps()) in getPreferredAddressingMode()
432 if ((ST->hasMVEIntegerOps() && in getCastInstrCost()
1217 if (ST->hasMVEIntegerOps()) { in getShuffleCost()
1441 if (ST->hasMVEIntegerOps()) { in getMaskedMemoryOpCost()
1652 if (ST->hasMVEIntegerOps()) in getIntrinsicInstrCost()
1659 if (!ST->hasMVEIntegerOps()) in getIntrinsicInstrCost()
1679 if (!ST->hasMVEIntegerOps()) in getIntrinsicInstrCost()
1750 return !ST->hasMVEIntegerOps(); in isLoweredToCall()
2091 if (!ST->hasMVEIntegerOps()) in preferPredicateOverEpilogue()
2246 if (!ST->hasMVEIntegerOps()) in preferInLoopReduction()
[all …]
H A DARMTargetTransformInfo.h149 if (ST->hasMVEIntegerOps()) in getNumberOfRegisters()
166 if (ST->hasMVEIntegerOps()) in getRegisterBitWidth()
H A DARMSelectionDAGInfo.cpp177 if (Subtarget.hasMVEIntegerOps() && in EmitTargetCodeForMemcpy()
308 if (Subtarget.hasMVEIntegerOps() && in EmitTargetCodeForMemset()
H A DMVEVPTBlockPass.cpp318 if (!STI.isThumb2() || !STI.hasMVEIntegerOps()) in runOnMachineFunction()
H A DARMISelLowering.cpp784 if (Subtarget->hasMVEIntegerOps()) in ARMTargetLowering()
1146 if (Subtarget->hasMVEIntegerOps()) in ARMTargetLowering()
6511 if (ST->hasMVEIntegerOps()) { in Expand64BitShift()
7614 if (!ST->hasMVEIntegerOps()) in LowerBUILD_VECTORToVIDUP()
8342 assert(ST->hasMVEIntegerOps() && in LowerVECTOR_SHUFFLE_i1()
8598 if (ST->hasMVEIntegerOps()) { in LowerVECTOR_SHUFFLE()
8714 if (ST->hasMVEIntegerOps()) in LowerVECTOR_SHUFFLE()
9925 if (!ST->hasMVEIntegerOps()) in LowerVecReduce()
15971 if (!ST->hasMVEIntegerOps()) in PerformVECREDUCE_ADDCombine()
16740 if (ST->hasMVEIntegerOps()) in PerformExtendCombine()
[all …]
H A DMVELaneInterleavingPass.cpp377 if (!ST->hasMVEIntegerOps()) in runOnFunction()
H A DMVETailPredication.cpp142 if (!ST->hasMVEIntegerOps() || !ST->hasV8_1MMainlineOps()) { in runOnLoop()
H A DARMSubtarget.h624 bool hasMVEIntegerOps() const { return HasMVEIntegerOps; } in hasMVEIntegerOps() function
H A DARMPredicates.td32 def HasMVEInt : Predicate<"Subtarget->hasMVEIntegerOps()">,
H A DARMRegisterInfo.td471 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();
511 return 1 + MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps();
H A DMVEGatherScatterLowering.cpp1214 if (!ST->hasMVEIntegerOps()) in runOnFunction()
H A DARMISelDAGToDAG.cpp3071 if (!Subtarget->hasMVEIntegerOps()) in tryInsertVectorElt()
3979 if (Subtarget->hasMVEIntegerOps() && tryMVEIndexedLoad(N)) in Select()
3993 if (Subtarget->hasMVEIntegerOps() && tryMVEIndexedLoad(N)) in Select()
H A DARMBaseInstrInfo.cpp1209 Subtarget.hasMVEIntegerOps()) { in storeRegToStackSlot()
1443 Subtarget.hasMVEIntegerOps()) { in loadRegFromStackSlot()