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Searched refs:hasBWI (Results 1 – 10 of 10) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86Subtarget.h743 bool hasBWI() const { return HasBWI; } in hasBWI() function
805 return hasBWI() && canExtendTo512DQ(); in canExtendTo512BW()
815 return hasBWI() && useAVX512Regs(); in useBWIRegs()
H A DX86TargetTransformInfo.cpp326 ST->hasBWI()) { in getArithmeticInstrCost()
414 ST->hasBWI()) { in getArithmeticInstrCost()
531 if (ST->hasBWI()) in getArithmeticInstrCost()
599 if (ST->hasBWI()) in getArithmeticInstrCost()
1237 if (ST->hasBWI()) in getShuffleCost()
2221 if (ST->hasBWI()) in getCastInstrCost()
2267 if (ST->hasBWI()) in getCastInstrCost()
2283 if (ST->hasBWI()) in getCastInstrCost()
2509 if (ST->hasBWI()) in getCmpSelInstrCost()
4074 if (ST->hasBWI()) in getMinMaxCost()
[all …]
H A DX86DomainReassignment.cpp652 if (STI->hasBWI()) { in initConverters()
734 if (!STI->hasAVX512() || !STI->hasBWI()) in runOnMachineFunction()
H A DX86PartialReduction.cpp219 if (ST->hasBWI() && NumElts >= 64) { in trySADReplacement()
H A DX86ISelLowering.cpp1919 if (Subtarget.hasBWI()) { in X86TargetLowering()
2109 !Subtarget.hasBWI()) in getPreferredVectorAction()
10238 if (Subtarget.hasBWI()) in createVariablePermute()
11695 !Subtarget.hasBWI()) in lowerShuffleWithVPMOV()
17394 if (Subtarget.hasBWI()) in lowerV16I16Shuffle()
17861 if (Subtarget.hasBWI()) in lowerV8I64Shuffle()
17925 if (Subtarget.hasBWI()) in lowerV16I32Shuffle()
20896 if (!Subtarget.hasBWI()) { in LowerZERO_EXTEND_Mask()
21068 if (Subtarget.hasBWI()) { in LowerTruncateVecI1()
24422 !Subtarget.hasBWI())) { in LowerStore()
[all …]
H A DX86LegalizerInfo.cpp540 if (!(Subtarget.hasAVX512() && Subtarget.hasBWI())) in setLegalizerInfoAVX512BW()
H A DX86FrameLowering.cpp2500 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1; in assignCalleeSavedSpillSlots()
2580 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1; in spillCalleeSavedRegisters()
2660 VT = STI.hasBWI() ? MVT::v64i1 : MVT::v16i1; in restoreCalleeSavedRegisters()
H A DX86InstrInfo.cpp3429 assert(Subtarget.hasBWI()); in CopyToFromAsymmetricReg()
3433 return Subtarget.hasBWI() ? X86::KMOVDrk : X86::KMOVWrk; in CopyToFromAsymmetricReg()
3442 assert(Subtarget.hasBWI()); in CopyToFromAsymmetricReg()
3446 return Subtarget.hasBWI() ? X86::KMOVDkr : X86::KMOVWkr; in CopyToFromAsymmetricReg()
3556 Opc = Subtarget.hasBWI() ? X86::KMOVQkk : X86::KMOVWkk; in copyPhysReg()
3624 assert(STI.hasBWI() && "KMOVD requires BWI"); in getLoadStoreRegOpcode()
3652 assert(STI.hasBWI() && "KMOVQ requires BWI"); in getLoadStoreRegOpcode()
H A DX86InstrInfo.td912 def HasBWI : Predicate<"Subtarget->hasBWI()">;
913 def NoBWI : Predicate<"!Subtarget->hasBWI()">;
916 def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">;
H A DX86ISelDAGToDAG.cpp916 if (!Subtarget->hasBWI() && (VT == MVT::v32i16 || VT == MVT::v64i8)) { in PreprocessISelDAG()
940 if (!Subtarget->hasBWI() && (VT == MVT::v32i16 || VT == MVT::v64i8)) { in PreprocessISelDAG()