1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2000 Michael Smith 5 * Copyright (c) 2000 BSDi 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Section numbers in this document refer to the Mylex "Firmware Software Interface" 34 * document ('FSI'), revision 0.11 04/11/00 unless otherwise qualified. 35 * 36 * Reference is made to the Mylex "Programming Guide for 6.x Controllers" document 37 * ('PG6'), document #771242 revision 0.02, 04/11/00 38 * 39 * Note that fields marked N/A are not supported by the PCI controllers, but are 40 * defined here to hold place in datastructures that are shared with the SCSI 41 * controllers. Items not relevant to PCI controllers are not described here. 42 * 43 * Ordering of items in this file is a little odd due to the constraints of 44 * nested declarations. 45 */ 46 47 /* 48 * 2.1 (Scatter Gather List Format) 49 */ 50 struct mly_sg_entry { 51 u_int64_t physaddr; 52 u_int64_t length; 53 } __packed; 54 55 /* 56 * 5.2 System Device Access 57 * 58 * This is corroborated by the layout of the MDACIOCTL_GETCONTROLLERINFO data 59 * in 21.8 60 */ 61 #define MLY_MAX_CHANNELS 6 62 #define MLY_MAX_TARGETS 16 63 #define MLY_MAX_LUNS 1 64 65 /* 66 * 8.1 Different Device States 67 */ 68 #define MLY_DEVICE_STATE_OFFLINE 0x08 /* DEAD/OFFLINE */ 69 #define MLY_DEVICE_STATE_UNCONFIGURED 0x00 70 #define MLY_DEVICE_STATE_ONLINE 0x01 71 #define MLY_DEVICE_STATE_CRITICAL 0x09 72 #define MLY_DEVICE_STATE_WRITEONLY 0x03 73 #define MLY_DEVICE_STATE_STANDBY 0x21 74 #define MLY_DEVICE_STATE_MISSING 0x04 /* or-ed with (ONLINE or WRITEONLY or STANDBY) */ 75 76 /* 77 * 8.2 Device Type Field definitions 78 */ 79 #define MLY_DEVICE_TYPE_RAID0 0x0 /* RAID 0 */ 80 #define MLY_DEVICE_TYPE_RAID1 0x1 /* RAID 1 */ 81 #define MLY_DEVICE_TYPE_RAID3 0x3 /* RAID 3 right asymmetric parity */ 82 #define MLY_DEVICE_TYPE_RAID5 0x5 /* RAID 5 right asymmetric parity */ 83 #define MLY_DEVICE_TYPE_RAID6 0x6 /* RAID 6 (Mylex RAID 6) */ 84 #define MLY_DEVICE_TYPE_RAID7 0x7 /* RAID 7 (JBOD) */ 85 #define MLY_DEVICE_TYPE_NEWSPAN 0x8 /* New Mylex SPAN */ 86 #define MLY_DEVICE_TYPE_RAID3F 0x9 /* RAID 3 fixed parity */ 87 #define MLY_DEVICE_TYPE_RAID3L 0xb /* RAID 3 left symmetric parity */ 88 #define MLY_DEVICE_TYPE_SPAN 0xc /* current spanning implementation */ 89 #define MLY_DEVICE_TYPE_RAID5L 0xd /* RAID 5 left symmetric parity */ 90 #define MLY_DEVICE_TYPE_RAIDE 0xe /* RAID E (concatenation) */ 91 #define MLY_DEVICE_TYPE_PHYSICAL 0xf /* physical device */ 92 93 /* 94 * 8.3 Stripe Size 95 */ 96 #define MLY_STRIPE_ZERO 0x0 /* no stripe (RAID 1, RAID 7, etc) */ 97 #define MLY_STRIPE_512b 0x1 98 #define MLY_STRIPE_1k 0x2 99 #define MLY_STRIPE_2k 0x3 100 #define MLY_STRIPE_4k 0x4 101 #define MLY_STRIPE_8k 0x5 102 #define MLY_STRIPE_16k 0x6 103 #define MLY_STRIPE_32k 0x7 104 #define MLY_STRIPE_64k 0x8 105 #define MLY_STRIPE_128k 0x9 106 #define MLY_STRIPE_256k 0xa 107 #define MLY_STRIPE_512k 0xb 108 #define MLY_STRIPE_1m 0xc 109 110 /* 111 * 8.4 Cacheline Size 112 */ 113 #define MLY_CACHELINE_ZERO 0x0 /* caching cannot be enabled */ 114 #define MLY_CACHELINE_512b 0x1 115 #define MLY_CACHELINE_1k 0x2 116 #define MLY_CACHELINE_2k 0x3 117 #define MLY_CACHELINE_4k 0x4 118 #define MLY_CACHELINE_8k 0x5 119 #define MLY_CACHELINE_16k 0x6 120 #define MLY_CACHELINE_32k 0x7 121 #define MLY_CACHELINE_64k 0x8 122 123 /* 124 * 8.5 Read/Write control 125 */ 126 #define MLY_RWCtl_INITTED (1<<7) /* if set, the logical device is initialised */ 127 /* write control */ 128 #define MLY_RWCtl_WCD (0) /* write cache disabled */ 129 #define MLY_RWCtl_WDISABLE (1<<3) /* writing disabled */ 130 #define MLY_RWCtl_WCE (2<<3) /* write cache enabled */ 131 #define MLY_RWCtl_IWCE (3<<3) /* intelligent write cache enabled */ 132 /* read control */ 133 #define MLY_RWCtl_RCD (0) /* read cache is disabled */ 134 #define MLY_RWCtl_RCE (1) /* read cache enabled */ 135 #define MLY_RWCtl_RAHEAD (2) /* readahead enabled */ 136 #define MLY_RWCtl_IRAHEAD (3) /* intelligent readahead enabled */ 137 138 /* 139 * 9.0 LUN Map Format 140 */ 141 struct mly_lun_map { 142 u_int8_t res1:4; 143 u_int8_t host_port_mapped:1; /* this system drive visible to host on this controller/port combination */ 144 u_int8_t tid_valid:1; /* target ID valid */ 145 u_int8_t hid_valid:1; /* host ID valid */ 146 u_int8_t lun_valid:1; /* LUN valid */ 147 u_int8_t res2; 148 u_int8_t lun; /* LUN */ 149 u_int8_t tid; /* TID */ 150 u_int8_t hid[32]; /* HID (one bit for each host) */ 151 } __packed; 152 153 /* 154 * 10.1 Controller Parameters 155 */ 156 struct mly_param_controller { 157 u_int8_t rdahen:1; /* N/A */ 158 u_int8_t bilodly:1; /* N/A */ 159 u_int8_t fua_disable:1; 160 u_int8_t reass1s:1; /* N/A */ 161 u_int8_t truvrfy:1; /* N/A */ 162 u_int8_t dwtvrfy:1; /* N/A */ 163 u_int8_t background_initialisation:1; 164 u_int8_t clustering:1; /* N/A */ 165 166 u_int8_t bios_disable:1; 167 u_int8_t boot_from_cdrom:1; 168 u_int8_t drive_coercion:1; 169 u_int8_t write_same_disable:1; 170 u_int8_t hba_mode:1; /* N/A */ 171 u_int8_t bios_geometry:2; 172 #define MLY_BIOSGEOM_2G 0x0 173 #define MLY_BIOSGEOM_8G 0x1 174 u_int8_t res1:1; /* N/A */ 175 176 u_int8_t res2[2]; /* N/A */ 177 178 u_int8_t v_dec:1; 179 u_int8_t safte:1; /* N/A */ 180 u_int8_t ses:1; /* N/A */ 181 u_int8_t res3:2; /* N/A */ 182 u_int8_t v_arm:1; 183 u_int8_t v_ofm:1; 184 u_int8_t res4:1; /* N/A */ 185 186 u_int8_t rebuild_check_rate; 187 u_int8_t cache_line_size; /* see 8.4 */ 188 u_int8_t oem_code; 189 #define MLY_OEM_MYLEX 0x00 190 #define MLY_OEM_IBM 0x08 191 #define MLY_OEM_HP 0x0a 192 #define MLY_OEM_DEC 0x0c 193 #define MLY_OEM_SIEMENS 0x10 194 #define MLY_OEM_INTEL 0x12 195 u_int8_t spinup_mode; 196 #define MLY_SPIN_AUTO 0 197 #define MLY_SPIN_PWRSPIN 1 198 #define MLY_SPIN_WSSUSPIN 2 199 u_int8_t spinup_devices; 200 u_int8_t spinup_interval; 201 u_int8_t spinup_wait_time; 202 203 u_int8_t res5:3; /* N/A */ 204 u_int8_t vutursns:1; /* N/A */ 205 u_int8_t dccfil:1; /* N/A */ 206 u_int8_t nopause:1; /* N/A */ 207 u_int8_t disqfull:1; /* N/A */ 208 u_int8_t disbusy:1; /* N/A */ 209 210 u_int8_t res6:2; /* N/A */ 211 u_int8_t failover_node_name; /* N/A */ 212 u_int8_t res7:1; /* N/A */ 213 u_int8_t ftopo:3; /* N/A */ 214 u_int8_t disable_ups:1; /* N/A */ 215 216 u_int8_t res8:1; /* N/A */ 217 u_int8_t propagate_reset:1; /* N/A */ 218 u_int8_t nonstd_mp_reset:1; /* N/A */ 219 u_int8_t res9:5; /* N/A */ 220 221 u_int8_t res10; /* N/A */ 222 u_int8_t serial_port_baud_rate; /* N/A */ 223 u_int8_t serial_port_control; /* N/A */ 224 u_int8_t change_stripe_ok_developer_flag_only; /* N/A */ 225 226 u_int8_t small_large_host_transfers:2; /* N/A */ 227 u_int8_t frame_control:2; /* N/A */ 228 u_int8_t pci_latency_control:2; /* N/A */ 229 u_int8_t treat_lip_as_reset:1; /* N/A */ 230 u_int8_t res11:1; /* N/A */ 231 232 u_int8_t ms_autorest:1; /* N/A */ 233 u_int8_t res12:7; /* N/A */ 234 235 u_int8_t ms_aa_fsim:1; /* N/A */ 236 u_int8_t ms_aa_ccach:1; /* N/A */ 237 u_int8_t ms_aa_fault_signals:1; /* N/A */ 238 u_int8_t ms_aa_c4_faults:1; /* N/A */ 239 u_int8_t ms_aa_host_reset_delay_mask:4; /* N/A */ 240 241 u_int8_t ms_flg_simplex_no_rstcom:1; /* N/A */ 242 u_int8_t res13:7; /* N/A */ 243 244 u_int8_t res14; /* N/A */ 245 u_int8_t hardloopid[2][2]; /* N/A */ 246 u_int8_t ctrlname[2][16+1]; /* N/A */ 247 u_int8_t initiator_id; 248 u_int8_t startup_option; 249 #define MLY_STARTUP_IF_NO_CHANGE 0x0 250 #define MLY_STARTUP_IF_NO_LUN_CHANGE 0x1 251 #define MLY_STARTUP_IF_NO_LUN_OFFLINE 0x2 252 #define MLY_STARTUP_IF_LUN0_NO_CHANGE 0x3 253 #define MLY_STARTUP_IF_LUN0_NOT_OFFLINE 0x4 254 #define MLY_STARTUP_ALWAYS 0x5 255 256 u_int8_t res15[62]; 257 } __packed; 258 259 /* 260 * 10.2 Physical Device Parameters 261 */ 262 struct mly_param_physical_device { 263 u_int16_t tags; 264 u_int16_t speed; 265 u_int8_t width; 266 u_int8_t combing:1; 267 u_int8_t res1:7; 268 u_int8_t res2[3]; 269 } __packed; 270 271 /* 272 * 10.3 Logical Device Parameters 273 */ 274 struct mly_param_logical_device { 275 u_int8_t type; /* see 8.2 */ 276 u_int8_t state; /* see 8.1 */ 277 u_int16_t raid_device; 278 u_int8_t res1; 279 u_int8_t bios_geometry; /* BIOS control word? */ 280 u_int8_t stripe_size; /* see 8.3 */ 281 u_int8_t read_write_control; /* see 8.5 */ 282 u_int8_t res2[8]; 283 } __packed; 284 285 /* 286 * 12.3 Health Status Buffer 287 * 288 * Pad to 128 bytes. 289 */ 290 struct mly_health_status { 291 u_int32_t uptime_us; /* N/A */ 292 u_int32_t uptime_ms; /* N/A */ 293 u_int32_t realtime; /* N/A */ 294 u_int32_t res1; /* N/A */ 295 u_int32_t change_counter; 296 u_int32_t res2; /* N/A */ 297 u_int32_t debug_message_index; /* N/A */ 298 u_int32_t bios_message_index; /* N/A */ 299 u_int32_t trace_page; /* N/A */ 300 u_int32_t profiler_page; /* N/A */ 301 u_int32_t next_event; 302 u_int8_t res3[4 + 16 + 64]; /* N/A */ 303 } __packed; 304 305 /* 306 * 14.2 Timeout Bit Format 307 */ 308 struct mly_timeout { 309 u_int8_t value:6; 310 u_int8_t scale:2; 311 #define MLY_TIMEOUT_SECONDS 0x0 312 #define MLY_TIMEOUT_MINUTES 0x1 313 #define MLY_TIMEOUT_HOURS 0x2 314 } __packed; 315 316 /* 317 * 14.3 Operation Device 318 */ 319 #define MLY_OPDEVICE_PHYSICAL_DEVICE 0x0 320 #define MLY_OPDEVICE_RAID_DEVICE 0x1 321 #define MLY_OPDEVICE_PHYSICAL_CHANNEL 0x2 322 #define MLY_OPDEVICE_RAID_CHANNEL 0x3 323 #define MLY_OPDEVICE_PHYSICAL_CONTROLLER 0x4 324 #define MLY_OPDEVICE_RAID_CONTROLLER 0x5 325 #define MLY_OPDEVICE_CONFIGURATION_GROUP 0x10 326 327 /* 328 * 14.4 Status Bit Format 329 * 330 * AKA Status Mailbox Format 331 * 332 * XXX format conflict between FSI and PG6 over the ordering of the 333 * status and sense length fields. 334 */ 335 struct mly_status { 336 u_int16_t command_id; 337 u_int8_t status; 338 u_int8_t sense_length; 339 int32_t residue; 340 } __packed; 341 342 /* 343 * 14.5 Command Control Bit (CCB) format 344 * 345 * This byte is unfortunately named. 346 */ 347 struct mly_command_control { 348 u_int8_t force_unit_access:1; 349 u_int8_t disable_page_out:1; 350 u_int8_t res1:1; 351 u_int8_t extended_sg_table:1; 352 u_int8_t data_direction:1; 353 #define MLY_CCB_WRITE 1 354 #define MLY_CCB_READ 0 355 u_int8_t res2:1; 356 u_int8_t no_auto_sense:1; 357 u_int8_t disable_disconnect:1; 358 } __packed; 359 360 /* 361 * 15.0 Commands 362 * 363 * We use the command names as given by Mylex 364 */ 365 #define MDACMD_MEMCOPY 0x1 /* memory to memory copy */ 366 #define MDACMD_SCSIPT 0x2 /* SCSI passthrough (small command) */ 367 #define MDACMD_SCSILCPT 0x3 /* SCSI passthrough (large command) */ 368 #define MDACMD_SCSI 0x4 /* SCSI command for logical/phyiscal device (small command) */ 369 #define MDACMD_SCSILC 0x5 /* SCSI command for logical/phyiscal device (large command) */ 370 #define MDACMD_IOCTL 0x20 /* Management command */ 371 #define MDACMD_IOCTLCHECK 0x23 /* Validate management command (not implemented) */ 372 373 /* 374 * 16.0 IOCTL command 375 * 376 * We use the IOCTL names as given by Mylex 377 * Note that only ioctls supported by the PCI controller family are listed 378 */ 379 #define MDACIOCTL_GETCONTROLLERINFO 0x1 380 #define MDACIOCTL_GETLOGDEVINFOVALID 0x3 381 #define MDACIOCTL_GETPHYSDEVINFOVALID 0x5 382 #define MDACIOCTL_GETCONTROLLERSTATISTICS 0xb 383 #define MDACIOCTL_GETLOGDEVSTATISTICS 0xd 384 #define MDACIOCTL_GETPHYSDEVSTATISTICS 0xf 385 #define MDACIOCTL_GETHEALTHSTATUS 0x11 386 #define MDACIOCTL_GETEVENT 0x15 387 /* flash update */ 388 #define MDACIOCTL_STOREIMAGE 0x2c 389 #define MDACIOCTL_READIMAGE 0x2d 390 #define MDACIOCTL_FLASHIMAGES 0x2e 391 /* battery backup unit */ 392 #define MDACIOCTL_GET_SUBSYSTEM_DATA 0x70 393 #define MDACIOCTL_SET_SUBSYSTEM_DATA 0x71 394 /* non-data commands */ 395 #define MDACIOCTL_STARTDISOCVERY 0x81 396 #define MDACIOCTL_SETRAIDDEVSTATE 0x82 397 #define MDACIOCTL_INITPHYSDEVSTART 0x84 398 #define MDACIOCTL_INITPHYSDEVSTOP 0x85 399 #define MDACIOCTL_INITRAIDDEVSTART 0x86 400 #define MDACIOCTL_INITRAIDDEVSTOP 0x87 401 #define MDACIOCTL_REBUILDRAIDDEVSTART 0x88 402 #define MDACIOCTL_REBUILDRAIDDEVSTOP 0x89 403 #define MDACIOCTL_MAKECONSISTENTDATASTART 0x8a 404 #define MDACIOCTL_MAKECONSISTENTDATASTOP 0x8b 405 #define MDACIOCTL_CONSISTENCYCHECKSTART 0x8c 406 #define MDACIOCTL_CONSISTENCYCHECKSTOP 0x8d 407 #define MDACIOCTL_SETMEMORYMAILBOX 0x8e 408 #define MDACIOCTL_RESETDEVICE 0x90 409 #define MDACIOCTL_FLUSHDEVICEDATA 0x91 410 #define MDACIOCTL_PAUSEDEVICE 0x92 411 #define MDACIOCTL_UNPAUSEDEVICE 0x93 412 #define MDACIOCTL_LOCATEDEVICE 0x94 413 #define MDACIOCTL_SETMASTERSLAVEMODE 0x95 414 #define MDACIOCTL_SETREALTIMECLOCK 0xac 415 /* RAID configuration */ 416 #define MDACIOCTL_CREATENEWCONF 0xc0 417 #define MDACIOCTL_DELETERAIDDEV 0xc1 418 #define MDACIOCTL_REPLACEINTERNALDEV 0xc2 419 #define MDACIOCTL_RENAMERAIDDEV 0xc3 420 #define MDACIOCTL_ADDNEWCONF 0xc4 421 #define MDACIOCTL_XLATEPHYSDEVTORAIDDEV 0xc5 422 #define MDACIOCTL_MORE 0xc6 423 #define MDACIOCTL_SETPHYSDEVPARAMETER 0xc8 424 #define MDACIOCTL_GETPHYSDEVPARAMETER 0xc9 425 #define MDACIOCTL_CLEARCONF 0xca 426 #define MDACIOCTL_GETDEVCONFINFO 0xcb 427 #define MDACIOCTL_GETGROUPCONFINFO 0xcc 428 #define MDACIOCTL_GETFREESPACELIST 0xcd 429 #define MDACIOCTL_GETLOGDEVPARAMETER 0xce 430 #define MDACIOCTL_SETLOGDEVPARAMETER 0xcf 431 #define MDACIOCTL_GETCONTROLLERPARAMETER 0xd0 432 #define MDACIOCTL_SETCONTRLLERPARAMETER 0xd1 433 #define MDACIOCTL_CLEARCONFSUSPMODE 0xd2 434 #define MDACIOCTL_GETBDT_FOR_SYSDRIVE 0xe0 435 436 /* 437 * 17.1.4 Data Transfer Memory Address Without SG List 438 */ 439 struct mly_short_transfer { 440 struct mly_sg_entry sg[2]; 441 } __packed; 442 443 /* 444 * 17.1.5 Data Transfer Memory Address With SG List 445 * 446 * Note that only the first s/g table is currently used. 447 */ 448 struct mly_sg_transfer { 449 u_int16_t entries[3]; 450 u_int16_t res1; 451 u_int64_t table_physaddr[3]; 452 } __packed; 453 454 /* 455 * 17.1.3 Data Transfer Memory Address Format 456 */ 457 union mly_command_transfer { 458 struct mly_short_transfer direct; 459 struct mly_sg_transfer indirect; 460 }; 461 462 /* 463 * 21.1 MDACIOCTL_SETREALTIMECLOCK 464 * 21.7 MDACIOCTL_GETHEALTHSTATUS 465 * 21.8 MDACIOCTL_GETCONTROLLERINFO 466 * 21.9 MDACIOCTL_GETLOGDEVINFOVALID 467 * 21.10 MDACIOCTL_GETPHYSDEVINFOVALID 468 * 21.11 MDACIOCTL_GETPHYSDEVSTATISTICS 469 * 21.12 MDACIOCTL_GETLOGDEVSTATISTICS 470 * 21.13 MDACIOCTL_GETCONTROLLERSTATISTICS 471 * 21.27 MDACIOCTL_GETBDT_FOR_SYSDRIVE 472 * 23.4 MDACIOCTL_CREATENEWCONF 473 * 23.5 MDACIOCTL_ADDNEWCONF 474 * 23.8 MDACIOCTL_GETDEVCONFINFO 475 * 23.9 MDACIOCTL_GETFREESPACELIST 476 * 24.1 MDACIOCTL_MORE 477 * 25.1 MDACIOCTL_GETPHYSDEVPARAMETER 478 * 25.2 MDACIOCTL_SETPHYSDEVPARAMETER 479 * 25.3 MDACIOCTL_GETLOGDEVPARAMETER 480 * 25.4 MDACIOCTL_SETLOGDEVPARAMETER 481 * 25.5 MDACIOCTL_GETCONTROLLERPARAMETER 482 * 25.6 MDACIOCTL_SETCONTROLLERPARAMETER 483 * 484 * These commands just transfer data 485 */ 486 struct mly_ioctl_param_data { 487 u_int8_t param[10]; 488 union mly_command_transfer transfer; 489 } __packed; 490 491 /* 492 * 21.2 MDACIOCTL_SETMEMORYMAILBOX 493 */ 494 struct mly_ioctl_param_setmemorymailbox { 495 u_int8_t health_buffer_size; 496 u_int8_t res1; 497 u_int64_t health_buffer_physaddr; 498 u_int64_t command_mailbox_physaddr; 499 u_int64_t status_mailbox_physaddr; 500 u_int64_t res2[2]; 501 } __packed; 502 503 /* 504 * 21.8.2 MDACIOCTL_GETCONTROLLERINFO: Data Format 505 */ 506 struct mly_ioctl_getcontrollerinfo { 507 u_int8_t res1; /* N/A */ 508 u_int8_t interface_type; 509 u_int8_t controller_type; 510 u_int8_t res2; /* N/A */ 511 u_int16_t interface_speed; 512 u_int8_t interface_width; 513 u_int8_t res3[9]; /* N/A */ 514 char interface_name[16]; 515 char controller_name[16]; 516 u_int8_t res4[16]; /* N/A */ 517 /* firmware release information */ 518 u_int8_t fw_major; 519 u_int8_t fw_minor; 520 u_int8_t fw_turn; 521 u_int8_t fw_build; 522 u_int8_t fw_day; 523 u_int8_t fw_month; 524 u_int8_t fw_century; 525 u_int8_t fw_year; 526 /* hardware release information */ 527 u_int8_t hw_revision; /* N/A */ 528 u_int8_t res5[3]; /* N/A */ 529 u_int8_t hw_release_day; /* N/A */ 530 u_int8_t hw_release_month; /* N/A */ 531 u_int8_t hw_release_century; /* N/A */ 532 u_int8_t hw_release_year; /* N/A */ 533 /* hardware manufacturing information */ 534 u_int8_t batch_number; /* N/A */ 535 u_int8_t res6; /* N/A */ 536 u_int8_t plant_number; 537 u_int8_t res7; 538 u_int8_t hw_manuf_day; 539 u_int8_t hw_manuf_month; 540 u_int8_t hw_manuf_century; 541 u_int8_t hw_manuf_year; 542 u_int8_t max_pdd_per_xldd; 543 u_int8_t max_ildd_per_xldd; 544 u_int16_t nvram_size; 545 u_int8_t max_number_of_xld; /* N/A */ 546 u_int8_t res8[3]; /* N/A */ 547 /* unique information per controller */ 548 char serial_number[16]; 549 u_int8_t res9[16]; /* N/A */ 550 /* vendor information */ 551 u_int8_t res10[3]; /* N/A */ 552 u_int8_t oem_information; 553 char vendor_name[16]; /* N/A */ 554 /* other physical/controller/operation information */ 555 u_int8_t bbu_present:1; 556 u_int8_t active_clustering:1; 557 u_int8_t res11:6; /* N/A */ 558 u_int8_t res12[3]; /* N/A */ 559 /* physical device scan information */ 560 u_int8_t physical_scan_active:1; 561 u_int8_t res13:7; /* N/A */ 562 u_int8_t physical_scan_channel; 563 u_int8_t physical_scan_target; 564 u_int8_t physical_scan_lun; 565 /* maximum command data transfer size */ 566 u_int16_t maximum_block_count; 567 u_int16_t maximum_sg_entries; 568 /* logical/physical device counts */ 569 u_int16_t logical_devices_present; 570 u_int16_t logical_devices_critical; 571 u_int16_t logical_devices_offline; 572 u_int16_t physical_devices_present; 573 u_int16_t physical_disks_present; 574 u_int16_t physical_disks_critical; /* N/A */ 575 u_int16_t physical_disks_offline; 576 u_int16_t maximum_parallel_commands; 577 /* channel and target ID information */ 578 u_int8_t physical_channels_present; 579 u_int8_t virtual_channels_present; 580 u_int8_t physical_channels_possible; 581 u_int8_t virtual_channels_possible; 582 u_int8_t maximum_targets_possible[16]; /* N/A (6 and up) */ 583 u_int8_t res14[12]; /* N/A */ 584 /* memory/cache information */ 585 u_int16_t memory_size; 586 u_int16_t cache_size; 587 u_int32_t valid_cache_size; /* N/A */ 588 u_int32_t dirty_cache_size; /* N/A */ 589 u_int16_t memory_speed; 590 u_int8_t memory_width; 591 u_int8_t memory_type:5; 592 u_int8_t res15:1; /* N/A */ 593 u_int8_t memory_parity:1; 594 u_int8_t memory_ecc:1; 595 char memory_information[16]; /* N/A */ 596 /* execution memory information */ 597 u_int16_t exmemory_size; 598 u_int16_t l2cache_size; /* N/A */ 599 u_int8_t res16[8]; /* N/A */ 600 u_int16_t exmemory_speed; 601 u_int8_t exmemory_width; 602 u_int8_t exmemory_type:5; 603 u_int8_t res17:1; /* N/A */ 604 u_int8_t exmemory_parity:1; 605 u_int8_t exmemory_ecc:1; 606 char exmemory_name[16]; /* N/A */ 607 /* CPU information */ 608 struct { 609 u_int16_t speed; 610 u_int8_t type; 611 u_int8_t number; 612 u_int8_t res1[12]; /* N/A */ 613 char name[16]; /* N/A */ 614 } cpu[2] __packed; 615 /* debugging/profiling/command time tracing information */ 616 u_int16_t profiling_page; /* N/A */ 617 u_int16_t profiling_programs; /* N/A */ 618 u_int16_t time_trace_page; /* N/A */ 619 u_int16_t time_trace_programs; /* N/A */ 620 u_int8_t res18[8]; /* N/A */ 621 /* error counters on physical devices */ 622 u_int16_t physical_device_bus_resets; /* N/A */ 623 u_int16_t physical_device_parity_errors; /* N/A */ 624 u_int16_t physical_device_soft_errors; /* N/A */ 625 u_int16_t physical_device_commands_failed; /* N/A */ 626 u_int16_t physical_device_miscellaneous_errors; /* N/A */ 627 u_int16_t physical_device_command_timeouts; /* N/A */ 628 u_int16_t physical_device_selection_timeouts; /* N/A */ 629 u_int16_t physical_device_retries; /* N/A */ 630 u_int16_t physical_device_aborts; /* N/A */ 631 u_int16_t physical_device_host_command_aborts; /* N/A */ 632 u_int16_t physical_device_PFAs_detected; /* N/A */ 633 u_int16_t physical_device_host_commands_failed; /* N/A */ 634 u_int8_t res19[8]; /* N/A */ 635 /* error counters on logical devices */ 636 u_int16_t logical_device_soft_errors; /* N/A */ 637 u_int16_t logical_device_commands_failed; /* N/A */ 638 u_int16_t logical_device_host_command_aborts; /* N/A */ 639 u_int16_t res20; /* N/A */ 640 /* error counters on controller */ 641 u_int16_t controller_parity_ecc_errors; 642 u_int16_t controller_host_command_aborts; /* N/A */ 643 u_int8_t res21[4]; /* N/A */ 644 /* long duration activity information */ 645 u_int16_t background_inits_active; 646 u_int16_t logical_inits_active; 647 u_int16_t physical_inits_active; 648 u_int16_t consistency_checks_active; 649 u_int16_t rebuilds_active; 650 u_int16_t MORE_active; 651 u_int16_t patrol_active; /* N/A */ 652 u_int8_t long_operation_status; /* N/A */ 653 u_int8_t res22; /* N/A */ 654 /* flash ROM information */ 655 u_int8_t flash_type; /* N/A */ 656 u_int8_t res23; /* N/A */ 657 u_int16_t flash_size; 658 u_int32_t flash_maximum_age; 659 u_int32_t flash_age; 660 u_int8_t res24[4]; /* N/A */ 661 char flash_name[16]; /* N/A */ 662 /* firmware runtime information */ 663 u_int8_t rebuild_rate; 664 u_int8_t background_init_rate; 665 u_int8_t init_rate; 666 u_int8_t consistency_check_rate; 667 u_int8_t res25[4]; /* N/A */ 668 u_int32_t maximum_dp; 669 u_int32_t free_dp; 670 u_int32_t maximum_iop; 671 u_int32_t free_iop; 672 u_int16_t maximum_comb_length; 673 u_int16_t maximum_configuration_groups; 674 u_int8_t installation_abort:1; 675 u_int8_t maintenance:1; 676 u_int8_t res26:6; /* N/A */ 677 u_int8_t res27[3]; /* N/A */ 678 u_int8_t res28[32 + 512]; /* N/A */ 679 } __packed; 680 681 /* 682 * 21.9.2 MDACIOCTL_GETLOGDEVINFOVALID 683 */ 684 struct mly_ioctl_getlogdevinfovalid { 685 u_int8_t res1; /* N/A */ 686 u_int8_t channel; 687 u_int8_t target; 688 u_int8_t lun; 689 u_int8_t state; /* see 8.1 */ 690 u_int8_t raid_level; /* see 8.2 */ 691 u_int8_t stripe_size; /* see 8.3 */ 692 u_int8_t cache_line_size; /* see 8.4 */ 693 u_int8_t read_write_control; /* see 8.5 */ 694 u_int8_t consistency_check:1; 695 u_int8_t rebuild:1; 696 u_int8_t make_consistent:1; 697 u_int8_t initialisation:1; 698 u_int8_t migration:1; 699 u_int8_t patrol:1; 700 u_int8_t res2:2; /* N/A */ 701 u_int8_t ar5_limit; 702 u_int8_t ar5_algo; 703 u_int16_t logical_device_number; 704 u_int16_t bios_control; 705 /* erorr counters */ 706 u_int16_t soft_errors; /* N/A */ 707 u_int16_t commands_failed; /* N/A */ 708 u_int16_t host_command_aborts; /* N/A */ 709 u_int16_t deferred_write_errors; /* N/A */ 710 u_int8_t res3[8]; /* N/A */ 711 /* device size information */ 712 u_int8_t res4[2]; /* N/A */ 713 u_int16_t device_block_size; 714 u_int32_t original_device_size; /* N/A */ 715 u_int32_t device_size; /* XXX "blocks or MB" Huh? */ 716 u_int8_t res5[4]; /* N/A */ 717 char device_name[32]; /* N/A */ 718 u_int8_t inquiry[36]; 719 u_int8_t res6[12]; /* N/A */ 720 u_int64_t last_read_block; /* N/A */ 721 u_int64_t last_written_block; /* N/A */ 722 u_int64_t consistency_check_block; 723 u_int64_t rebuild_block; 724 u_int64_t make_consistent_block; 725 u_int64_t initialisation_block; 726 u_int64_t migration_block; 727 u_int64_t patrol_block; /* N/A */ 728 u_int8_t res7[64]; /* N/A */ 729 } __packed; 730 731 /* 732 * 21.10.2 MDACIOCTL_GETPHYSDEVINFOVALID: Data Format 733 */ 734 struct mly_ioctl_getphysdevinfovalid { 735 u_int8_t res1; 736 u_int8_t channel; 737 u_int8_t target; 738 u_int8_t lun; 739 u_int8_t raid_ft:1; /* configuration status */ 740 u_int8_t res2:1; /* N/A */ 741 u_int8_t local:1; 742 u_int8_t res3:5; 743 u_int8_t host_dead:1; /* multiple host/controller status *//* N/A */ 744 u_int8_t host_connection_dead:1; /* N/A */ 745 u_int8_t res4:6; /* N/A */ 746 u_int8_t state; /* see 8.1 */ 747 u_int8_t width; 748 u_int16_t speed; 749 /* multiported physical device information */ 750 u_int8_t ports_available; /* N/A */ 751 u_int8_t ports_inuse; /* N/A */ 752 u_int8_t res5[4]; 753 u_int8_t ether_address[16]; /* N/A */ 754 u_int16_t command_tags; 755 u_int8_t consistency_check:1; /* N/A */ 756 u_int8_t rebuild:1; /* N/A */ 757 u_int8_t make_consistent:1; /* N/A */ 758 u_int8_t initialisation:1; 759 u_int8_t migration:1; /* N/A */ 760 u_int8_t patrol:1; /* N/A */ 761 u_int8_t res6:2; 762 u_int8_t long_operation_status; /* N/A */ 763 u_int8_t parity_errors; 764 u_int8_t soft_errors; 765 u_int8_t hard_errors; 766 u_int8_t miscellaneous_errors; 767 u_int8_t command_timeouts; /* N/A */ 768 u_int8_t retries; /* N/A */ 769 u_int8_t aborts; /* N/A */ 770 u_int8_t PFAs_detected; /* N/A */ 771 u_int8_t res7[6]; 772 u_int16_t block_size; 773 u_int32_t original_device_size; /* XXX "blocks or MB" Huh? */ 774 u_int32_t device_size; /* XXX "blocks or MB" Huh? */ 775 u_int8_t res8[4]; 776 char name[16]; /* N/A */ 777 u_int8_t res9[16 + 32]; 778 u_int8_t inquiry[36]; 779 u_int8_t res10[12 + 16]; 780 u_int64_t last_read_block; /* N/A */ 781 u_int64_t last_written_block; /* N/A */ 782 u_int64_t consistency_check_block; /* N/A */ 783 u_int64_t rebuild_block; /* N/A */ 784 u_int64_t make_consistent_block; /* N/A */ 785 u_int64_t initialisation_block; /* N/A */ 786 u_int64_t migration_block; /* N/A */ 787 u_int64_t patrol_block; /* N/A */ 788 u_int8_t res11[256]; 789 } __packed; 790 791 union mly_devinfo { 792 struct mly_ioctl_getlogdevinfovalid logdev; 793 struct mly_ioctl_getphysdevinfovalid physdev; 794 }; 795 796 /* 797 * 21.11.2 MDACIOCTL_GETPHYSDEVSTATISTICS: Data Format 798 * 21.12.2 MDACIOCTL_GETLOGDEVSTATISTICS: Data Format 799 */ 800 struct mly_ioctl_getdevstatistics { 801 u_int32_t uptime_ms; /* getphysedevstatistics only */ 802 u_int8_t res1[5]; /* N/A */ 803 u_int8_t channel; 804 u_int8_t target; 805 u_int8_t lun; 806 u_int16_t raid_device; /* getlogdevstatistics only */ 807 u_int8_t res2[2]; /* N/A */ 808 /* total read/write performance including cache data */ 809 u_int32_t total_reads; 810 u_int32_t total_writes; 811 u_int32_t total_read_size; 812 u_int32_t total_write_size; 813 /* cache read/write performance */ 814 u_int32_t cache_reads; /* N/A */ 815 u_int32_t cache_writes; /* N/A */ 816 u_int32_t cache_read_size; /* N/A */ 817 u_int32_t cache_write_size; /* N/A */ 818 /* commands active/wait information */ 819 u_int32_t command_waits_done; /* N/A */ 820 u_int16_t active_commands; /* N/A */ 821 u_int16_t waiting_commands; /* N/A */ 822 u_int8_t res3[8]; /* N/A */ 823 } __packed; 824 825 /* 826 * 21.13.2 MDACIOCTL_GETCONTROLLERSTATISTICS: Data Format 827 */ 828 struct mly_ioctl_getcontrollerstatistics { 829 u_int32_t uptime_ms; /* N/A */ 830 u_int8_t res1[12]; /* N/A */ 831 /* target physical device performance data information */ 832 u_int32_t target_physical_device_interrupts; /* N/A */ 833 u_int32_t target_physical_device_stray_interrupts; /* N/A */ 834 u_int8_t res2[8]; /* N/A */ 835 u_int32_t target_physical_device_reads; /* N/A */ 836 u_int32_t target_physical_device_writes; /* N/A */ 837 u_int32_t target_physical_device_read_size; /* N/A */ 838 u_int32_t target_physical_device_write_size; /* N/A */ 839 /* host system performance data information */ 840 u_int32_t host_system_interrupts; /* N/A */ 841 u_int32_t host_system_stray_interrupts; /* N/A */ 842 u_int32_t host_system_sent_interrupts; /* N/A */ 843 u_int8_t res3[4]; /* N/A */ 844 u_int32_t physical_device_reads; /* N/A */ 845 u_int32_t physical_device_writes; /* N/A */ 846 u_int32_t physical_device_read_size; /* N/A */ 847 u_int32_t physical_device_write_size; /* N/A */ 848 u_int32_t physical_device_cache_reads; /* N/A */ 849 u_int32_t physical_device_cache_writes; /* N/A */ 850 u_int32_t physical_device_cache_read_size; /* N/A */ 851 u_int32_t physical_device_cache_write_size; /* N/A */ 852 u_int32_t logical_device_reads; /* N/A */ 853 u_int32_t logical_device_writes; /* N/A */ 854 u_int32_t logical_device_read_size; /* N/A */ 855 u_int32_t logical_device_write_size; /* N/A */ 856 u_int32_t logical_device_cache_reads; /* N/A */ 857 u_int32_t logical_device_cache_writes; /* N/A */ 858 u_int32_t logical_device_cache_read_size; /* N/A */ 859 u_int32_t logical_device_cache_write_size; /* N/A */ 860 u_int16_t target_physical_device_commands_active; /* N/A */ 861 u_int16_t target_physical_device_commands_waiting; /* N/A */ 862 u_int16_t host_system_commands_active; /* N/A */ 863 u_int16_t host_system_commands_waiting; /* N/A */ 864 u_int8_t res4[48 + 64]; /* N/A */ 865 } __packed; 866 867 /* 868 * 21.2 MDACIOCTL_SETRAIDDEVSTATE 869 */ 870 struct mly_ioctl_param_setraiddevstate { 871 u_int8_t state; 872 } __packed; 873 874 /* 875 * 21.27.2 MDACIOCTL_GETBDT_FOR_SYSDRIVE: Data Format 876 */ 877 #define MLY_MAX_BDT_ENTRIES 1022 878 struct mly_ioctl_getbdt_for_sysdrive { 879 u_int32_t num_of_bdt_entries; 880 u_int32_t bad_data_block_address[MLY_MAX_BDT_ENTRIES]; 881 } __packed; 882 883 /* 884 * 22.1 Physical Device Definition (PDD) 885 */ 886 struct mly_pdd { 887 u_int8_t type; /* see 8.2 */ 888 u_int8_t state; /* see 8.1 */ 889 u_int16_t raid_device; 890 u_int32_t device_size; /* XXX "block or MB" Huh? */ 891 u_int8_t controller; 892 u_int8_t channel; 893 u_int8_t target; 894 u_int8_t lun; 895 u_int32_t start_address; 896 } __packed; 897 898 /* 899 * 22.2 RAID Device Use Definition (UDD) 900 */ 901 struct mly_udd { 902 u_int8_t res1; 903 u_int8_t state; /* see 8.1 */ 904 u_int16_t raid_device; 905 u_int32_t start_address; 906 } __packed; 907 908 /* 909 * RAID Device Definition (LDD) 910 */ 911 struct mly_ldd { 912 u_int8_t type; /* see 8.2 */ 913 u_int8_t state; /* see 8.1 */ 914 u_int16_t raid_device; 915 u_int32_t device_size; /* XXX "block or MB" Huh? */ 916 u_int8_t devices_used_count; 917 u_int8_t stripe_size; /* see 8.3 */ 918 u_int8_t cache_line_size; /* see 8.4 */ 919 u_int8_t read_write_control; /* see 8.5 */ 920 u_int32_t devices_used_size; /* XXX "block or MB" Huh? */ 921 u_int16_t devices_used[32]; /* XXX actual size of this field unknown! */ 922 } __packed; 923 924 /* 925 * Define a datastructure giving the smallest allocation that will hold 926 * a PDD, UDD or LDD for MDACIOCTL_GETDEVCONFINFO. 927 */ 928 struct mly_devconf_hdr { 929 u_int8_t type; /* see 8.2 */ 930 u_int8_t state; /* see 8.1 */ 931 u_int16_t raid_device; 932 }; 933 934 union mly_ioctl_devconfinfo { 935 struct mly_pdd pdd; 936 struct mly_udd udd; 937 struct mly_ldd ldd; 938 struct mly_devconf_hdr hdr; 939 }; 940 941 /* 942 * 22.3 MDACIOCTL_RENAMERAIDDEV 943 * 944 * XXX this command is listed as transferring data, but does not define the data. 945 */ 946 struct mly_ioctl_param_renameraiddev { 947 u_int8_t new_raid_device; 948 } __packed; 949 950 /* 951 * 23.6.2 MDACIOCTL_XLATEPHYSDEVTORAIDDEV 952 * 953 * XXX documentation suggests this format will change 954 */ 955 struct mly_ioctl_param_xlatephysdevtoraiddev { 956 u_int16_t raid_device; 957 u_int8_t res1[2]; 958 u_int8_t controller; 959 u_int8_t channel; 960 u_int8_t target; 961 u_int8_t lun; 962 } __packed; 963 964 /* 965 * 23.7 MDACIOCTL_GETGROUPCONFINFO 966 */ 967 struct mly_ioctl_param_getgroupconfinfo { 968 u_int16_t group; 969 u_int8_t res1[8]; 970 union mly_command_transfer transfer; 971 } __packed; 972 973 /* 974 * 23.9.2 MDACIOCTL_GETFREESPACELIST: Data Format 975 * 976 * The controller will populate as much of this structure as is provided, 977 * or as is required to fully list the free space available. 978 */ 979 struct mly_ioctl_getfreespacelist_entry { 980 u_int16_t raid_device; 981 u_int8_t res1[6]; 982 u_int32_t address; /* XXX "blocks or MB" Huh? */ 983 u_int32_t size; /* XXX "blocks or MB" Huh? */ 984 } __packed; 985 986 struct mly_ioctl_getfrespacelist { 987 u_int16_t returned_entries; 988 u_int16_t total_entries; 989 u_int8_t res1[12]; 990 struct mly_ioctl_getfreespacelist_entry space[0]; /* expand to suit */ 991 } __packed; 992 993 /* 994 * 27.1 MDACIOCTL_GETSUBSYSTEMDATA 995 * 27.2 MDACIOCTL_SETSUBSYSTEMDATA 996 * 997 * PCI controller only supports a limited subset of the possible operations. 998 * 999 * XXX where does the status end up? (the command transfers no data) 1000 */ 1001 struct mly_ioctl_param_subsystemdata { 1002 u_int8_t operation:4; 1003 #define MLY_BBU_GETSTATUS 0x00 1004 #define MLY_BBU_SET_THRESHOLD 0x00 /* minutes in param[0,1] */ 1005 u_int8_t subsystem:4; 1006 #define MLY_SUBSYSTEM_BBU 0x01 1007 u_int parameter[3]; /* only for SETSUBSYSTEMDATA */ 1008 } __packed; 1009 1010 struct mly_ioctl_getsubsystemdata_bbustatus { 1011 u_int16_t current_power; 1012 u_int16_t maximum_power; 1013 u_int16_t power_threshold; 1014 u_int8_t charge_level; 1015 u_int8_t hardware_version; 1016 u_int8_t battery_type; 1017 #define MLY_BBU_TYPE_UNKNOWN 0x00 1018 #define MLY_BBU_TYPE_NICAD 0x01 1019 #define MLY_BBU_TYPE_MISSING 0xfe 1020 u_int8_t res1; 1021 u_int8_t operation_status; 1022 #define MLY_BBU_STATUS_NO_SYNC 0x01 1023 #define MLY_BBU_STATUS_OUT_OF_SYNC 0x02 1024 #define MLY_BBU_STATUS_FIRST_WARNING 0x04 1025 #define MLY_BBU_STATUS_SECOND_WARNING 0x08 1026 #define MLY_BBU_STATUS_RECONDITIONING 0x10 1027 #define MLY_BBU_STATUS_DISCHARGING 0x20 1028 #define MLY_BBU_STATUS_FASTCHARGING 0x40 1029 u_int8_t res2; 1030 } __packed; 1031 1032 /* 1033 * 28.9 MDACIOCTL_RESETDEVICE 1034 * 28.10 MDACIOCTL_FLUSHDEVICEDATA 1035 * 28.11 MDACIOCTL_PAUSEDEVICE 1036 * 28.12 MDACIOCTL_UNPAUSEDEVICE 1037 */ 1038 struct mly_ioctl_param_deviceoperation { 1039 u_int8_t operation_device; /* see 14.3 */ 1040 } __packed; 1041 1042 /* 1043 * 31.1 Event Data Format 1044 */ 1045 struct mly_event { 1046 u_int32_t sequence_number; 1047 u_int32_t timestamp; 1048 u_int32_t code; 1049 u_int8_t controller; 1050 u_int8_t channel; 1051 u_int8_t target; /* also enclosure */ 1052 u_int8_t lun; /* also enclosure unit */ 1053 u_int8_t res1[4]; 1054 u_int32_t param; 1055 u_int8_t sense[40]; 1056 } __packed; 1057 1058 /* 1059 * 31.2 MDACIOCTL_GETEVENT 1060 */ 1061 struct mly_ioctl_param_getevent { 1062 u_int16_t sequence_number_low; 1063 u_int8_t res1[8]; 1064 union mly_command_transfer transfer; 1065 } __packed; 1066 1067 union mly_ioctl_param { 1068 struct mly_ioctl_param_data data; 1069 struct mly_ioctl_param_setmemorymailbox setmemorymailbox; 1070 struct mly_ioctl_param_setraiddevstate setraiddevstate; 1071 struct mly_ioctl_param_renameraiddev renameraiddev; 1072 struct mly_ioctl_param_xlatephysdevtoraiddev xlatephysdevtoraiddev; 1073 struct mly_ioctl_param_getgroupconfinfo getgroupconfinfo; 1074 struct mly_ioctl_param_subsystemdata subsystemdata; 1075 struct mly_ioctl_param_deviceoperation deviceoperation; 1076 struct mly_ioctl_param_getevent getevent; 1077 }; 1078 1079 /* 1080 * 19 SCSI Command Format 1081 */ 1082 struct mly_command_address_physical { 1083 u_int8_t lun; 1084 u_int8_t target; 1085 u_int8_t channel:3; 1086 u_int8_t controller:5; 1087 } __packed; 1088 1089 struct mly_command_address_logical { 1090 u_int16_t logdev; 1091 u_int8_t res1:3; 1092 u_int8_t controller:5; 1093 } __packed; 1094 1095 union mly_command_address { 1096 struct mly_command_address_physical phys; 1097 struct mly_command_address_logical log; 1098 }; 1099 1100 struct mly_command_generic { 1101 u_int16_t command_id; 1102 u_int8_t opcode; 1103 struct mly_command_control command_control; 1104 u_int32_t data_size; 1105 u_int64_t sense_buffer_address; 1106 union mly_command_address addr; 1107 struct mly_timeout timeout; 1108 u_int8_t maximum_sense_size; 1109 u_int8_t res1[11]; 1110 union mly_command_transfer transfer; 1111 } __packed; 1112 1113 1114 /* 1115 * 19.1 MDACMD_SCSI & MDACMD_SCSIPT 1116 */ 1117 #define MLY_CMD_SCSI_SMALL_CDB 10 1118 struct mly_command_scsi_small { 1119 u_int16_t command_id; 1120 u_int8_t opcode; 1121 struct mly_command_control command_control; 1122 u_int32_t data_size; 1123 u_int64_t sense_buffer_address; 1124 union mly_command_address addr; 1125 struct mly_timeout timeout; 1126 u_int8_t maximum_sense_size; 1127 u_int8_t cdb_length; 1128 u_int8_t cdb[MLY_CMD_SCSI_SMALL_CDB]; 1129 union mly_command_transfer transfer; 1130 } __packed; 1131 1132 /* 1133 * 19.2 MDACMD_SCSILC & MDACMD_SCSILCPT 1134 */ 1135 struct mly_command_scsi_large { 1136 u_int16_t command_id; 1137 u_int8_t opcode; 1138 struct mly_command_control command_control; 1139 u_int32_t data_size; 1140 u_int64_t sense_buffer_address; 1141 union mly_command_address addr; 1142 struct mly_timeout timeout; 1143 u_int8_t maximum_sense_size; 1144 u_int8_t cdb_length; 1145 u_int16_t res1; 1146 u_int64_t cdb_physaddr; 1147 union mly_command_transfer transfer; 1148 } __packed; 1149 1150 /* 1151 * 20.1 IOCTL Command Format: Internal Bus 1152 */ 1153 struct mly_command_ioctl { 1154 u_int16_t command_id; 1155 u_int8_t opcode; 1156 struct mly_command_control command_control; 1157 u_int32_t data_size; 1158 u_int64_t sense_buffer_address; 1159 union mly_command_address addr; 1160 struct mly_timeout timeout; 1161 u_int8_t maximum_sense_size; 1162 u_int8_t sub_ioctl; 1163 union mly_ioctl_param param; 1164 } __packed; 1165 1166 /* 1167 * PG6: 8.2.2 1168 */ 1169 struct mly_command_mmbox { 1170 u_int32_t flag; 1171 u_int8_t data[60]; 1172 } __packed; 1173 1174 union mly_command_packet { 1175 struct mly_command_generic generic; 1176 struct mly_command_scsi_small scsi_small; 1177 struct mly_command_scsi_large scsi_large; 1178 struct mly_command_ioctl ioctl; 1179 struct mly_command_mmbox mmbox; 1180 }; 1181 1182 /* 1183 * PG6: 5.3 1184 */ 1185 #define MLY_I960RX_COMMAND_MAILBOX 0x10 1186 #define MLY_I960RX_STATUS_MAILBOX 0x18 1187 #define MLY_I960RX_IDBR 0x20 1188 #define MLY_I960RX_ODBR 0x2c 1189 #define MLY_I960RX_ERROR_STATUS 0x2e 1190 #define MLY_I960RX_INTERRUPT_STATUS 0x30 1191 #define MLY_I960RX_INTERRUPT_MASK 0x34 1192 1193 #define MLY_STRONGARM_COMMAND_MAILBOX 0x50 1194 #define MLY_STRONGARM_STATUS_MAILBOX 0x58 1195 #define MLY_STRONGARM_IDBR 0x60 1196 #define MLY_STRONGARM_ODBR 0x61 1197 #define MLY_STRONGARM_ERROR_STATUS 0x63 1198 #define MLY_STRONGARM_INTERRUPT_STATUS 0x30 1199 #define MLY_STRONGARM_INTERRUPT_MASK 0x34 1200 1201 /* 1202 * PG6: 5.4.3 Doorbell 0 1203 */ 1204 #define MLY_HM_CMDSENT (1<<0) 1205 #define MLY_HM_STSACK (1<<1) 1206 #define MLY_SOFT_RST (1<<3) 1207 #define MLY_AM_CMDSENT (1<<4) 1208 1209 /* 1210 * PG6: 5.4.4 Doorbell 1 1211 * 1212 * Note that the documentation claims that these bits are set when the 1213 * status queue(s) are empty, whereas the Linux driver and experience 1214 * suggest they are set when there is status available. 1215 */ 1216 #define MLY_HM_STSREADY (1<<0) 1217 #define MLY_AM_STSREADY (1<<1) 1218 1219 /* 1220 * PG6: 5.4.6 Doorbell 3 1221 */ 1222 #define MLY_MSG_EMPTY (1<<3) 1223 #define MLY_MSG_SPINUP 0x08 1224 #define MLY_MSG_RACE_RECOVERY_FAIL 0x60 1225 #define MLY_MSG_RACE_IN_PROGRESS 0x70 1226 #define MLY_MSG_RACE_ON_CRITICAL 0xb0 1227 #define MLY_MSG_PARITY_ERROR 0xf0 1228 1229 /* 1230 * PG6: 5.4.8 Outbound Interrupt Mask 1231 */ 1232 #define MLY_INTERRUPT_MASK_DISABLE 0xff 1233 #define MLY_INTERRUPT_MASK_ENABLE (0xff & ~(1<<2)) 1234 1235 /* 1236 * PG6: 8.2 Advanced Mailbox Scheme 1237 * 1238 * Note that this must be allocated on a 4k boundary, and all internal 1239 * fields must also reside on a 4k boundary. 1240 * We could dynamically size this structure, but the extra effort 1241 * is probably unjustified. Note that these buffers do not need to be 1242 * adjacent - we just group them to simplify allocation of the bus-visible 1243 * buffer. 1244 * 1245 * XXX Note that for some reason, if MLY_MMBOX_COMMANDS is > 64, the controller 1246 * fails to respond to the command at (MLY_MMBOX_COMMANDS - 64). It's not 1247 * wrapping to 0 at this point (determined by experimentation). This is not 1248 * consistent with the Linux driver's implementation. 1249 * Whilst it's handy to have lots of room for status returns in case we end up 1250 * being slow getting back to completed commands, it seems unlikely that we 1251 * would get 64 commands ahead of the controller on the submissions side, so 1252 * the current workaround is to simply limit the command ring to 64 entries. 1253 */ 1254 union mly_status_packet { 1255 struct mly_status status; 1256 struct { 1257 u_int32_t flag; 1258 u_int8_t data[4]; 1259 } __packed mmbox; 1260 }; 1261 union mly_health_region { 1262 struct mly_health_status status; 1263 u_int8_t pad[1024]; 1264 }; 1265 1266 #define MLY_MMBOX_COMMANDS 64 1267 #define MLY_MMBOX_STATUS 512 1268 struct mly_mmbox { 1269 union mly_command_packet mmm_command[MLY_MMBOX_COMMANDS]; 1270 union mly_status_packet mmm_status[MLY_MMBOX_STATUS]; 1271 union mly_health_region mmm_health; 1272 } __packed; 1273