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Searched refs:getVT (Results 1 – 25 of 43) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/
H A DDAGISelMatcherEmitter.cpp670 << getEnumName(cast<EmitIntegerMatcher>(N)->getVT()) << ", "; in EmitMatcher()
679 << getEnumName(cast<EmitStringIntegerMatcher>(N)->getVT()) << ", " << Val in EmitMatcher()
690 OS << "OPC_EmitRegister2, " << getEnumName(Matcher->getVT()) << ", "; in EmitMatcher()
694 OS << "OPC_EmitRegister, " << getEnumName(Matcher->getVT()) << ", "; in EmitMatcher()
797 OS << getEnumName(EN->getVT(i)) << ", "; in EmitMatcher()
H A DDAGISelMatcher.h825 MVT::SimpleValueType getVT() const { return VT; } in getVT() function
849 MVT::SimpleValueType getVT() const { return VT; } in getVT() function
874 MVT::SimpleValueType getVT() const { return VT; } in getVT() function
1018 MVT::SimpleValueType getVT(unsigned i) const { in getVT() function
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DValueTypes.cpp526 MVT MVT::getVT(Type *Ty, bool HandleUnknown){ in getVT() function in MVT
549 getVT(VTy->getElementType(), /*HandleUnknown=*/ false), in getVT()
561 return MVT::getVT(Ty, HandleUnknown); in getEVT()
H A DTargetLoweringBase.cpp1853 return std::make_pair(InstructionCost::getInvalid(), MVT::getVT(Ty)); in getTypeLegalizationCost()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InterleavedAccess.cpp562 MVT VT = MVT::getVT(Shuffles[0]->getType()); in deinterleave8bitStride3()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp1008 EVT VT = cast<VTSDNode>(N)->getVT(); in RemoveNodeFromCSEMaps()
3156 EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in computeKnownBits()
3297 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in computeKnownBits()
3695 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); in ComputeNumSignBits()
3698 Tmp = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); in ComputeNumSignBits()
5727 EVT EVT = cast<VTSDNode>(N2)->getVT(); in getNode()
5739 EVT EVT = cast<VTSDNode>(N2)->getVT(); in getNode()
5783 assert(VT.isInteger() && cast<VTSDNode>(N2)->getVT().isInteger() && in getNode()
5791 assert(!cast<VTSDNode>(N2)->getVT().isVector() && in getNode()
5793 assert(cast<VTSDNode>(N2)->getVT().bitsLE(VT.getScalarType()) && in getNode()
[all …]
H A DSelectionDAGDumper.cpp686 OS << ":" << N->getVT().getEVTString(); in print_details()
H A DTargetLowering.cpp786 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in SimplifyMultipleUseDemandedBits()
1793 EVT ExVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in SimplifyDemandedBits()
2053 EVT ZVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in SimplifyDemandedBits()
3781 !isSExtCheaperThanZExt(cast<VTSDNode>(N0.getOperand(1))->getVT(), in SimplifySetCC()
3783 EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); in SimplifySetCC()
3886 cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1) in SimplifySetCC()
4730 MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true); in ParseConstraints()
4737 OpInfo.ConstraintVT = MVT::getVT(OpTy, true); in ParseConstraints()
8666 EVT SatVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); in expandFP_TO_INT_SAT()
H A DSelectionDAGISel.cpp2621 if (cast<VTSDNode>(N)->getVT() == VT) in CheckValueType()
2625 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(DL); in CheckValueType()
H A DLegalizeVectorOps.cpp982 EVT OrigTy = cast<VTSDNode>(Node->getOperand(1))->getVT(); in ExpandSEXTINREG()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp1463 : cast<VTSDNode>(N.getOperand(1))->getVT(); in DetectUseSxtw()
1532 if (T->getVT().getSizeInBits() == NumBits) { in keepsLowBits()
1605 return VN->getVT().getSizeInBits() <= 16; in isPositiveHalfWord()
H A DHexagonISelLowering.cpp1066 EVT OrigTy = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerSETCC()
2067 Info.memVT = MVT::getVT(ElTy); in getTgtMemIntrinsic()
2092 Info.memVT = MVT::getVT(VecTy); in getTgtMemIntrinsic()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp183 unsigned Width = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits(); in LowerSIGN_EXTEND_INREG()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Support/
H A DMachineValueType.h1402 static MVT getVT(Type *Ty, bool HandleUnknown = false);
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp387 LLT OldLLT(MVT::getVT(CurArgInfo.Ty)); in lowerReturn()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3384 EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerFP_TO_INT_SAT()
11233 Info.memVT = MVT::getVT(PtrTy->getElementType()); in getTgtMemIntrinsic()
11244 Info.memVT = MVT::getVT(PtrTy->getElementType()); in getTgtMemIntrinsic()
11272 Info.memVT = MVT::getVT(I.getType()); in getTgtMemIntrinsic()
11284 Info.memVT = MVT::getVT(I.getOperand(0)->getType()); in getTgtMemIntrinsic()
12489 return TypeNode->getVT(); in calculatePreExtendType()
13211 MemVT = cast<VTSDNode>(Src->getOperand(3))->getVT(); in performSVEAndCombine()
13228 MemVT = cast<VTSDNode>(Src->getOperand(4))->getVT(); in performSVEAndCombine()
15428 if ((TypeNode->getVT() == MVT::i8 && width == 8) in checkValueWidth()
15437 if ((TypeNode->getVT() == MVT::i8 && width == 8) in checkValueWidth()
[all …]
H A DAArch64ISelDAGToDAG.cpp589 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT(); in getExtendTypeForNode()
1910 unsigned Width = cast<VTSDNode>(N->getOperand(1))->getVT().getSizeInBits(); in isBitfieldExtractOpFromSExtInReg()
4952 return cast<VTSDNode>(Root->getOperand(3))->getVT(); in getMemVTFromNode()
4954 return cast<VTSDNode>(Root->getOperand(4))->getVT(); in getMemVTFromNode()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp869 MVT VT = MVT::getVT(Outs[I].Ty); in checkReturn()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.td880 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
884 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
H A DRISCVISelDAGToDAG.cpp1468 cast<VTSDNode>(N.getOperand(1))->getVT() == MVT::i32) { in selectSExti32()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp1754 cast<VTSDNode>(Op.getOperand(1).getNode())->getVT().getSimpleVT(); in LowerSIGN_EXTEND_INREG()
2142 EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); in LowerFP_TO_INT_SAT()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp1119 Info.memVT = MVT::getVT(CI.getArgOperand(0)->getType()); in getTgtMemIntrinsic()
1139 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
1154 Info.memVT = MVT::getVT(CI.getOperand(0)->getType()); in getTgtMemIntrinsic()
1169 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
1182 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
1193 Info.memVT = MVT::getVT(CI.getType()); // XXX: what is correct VT? in getTgtMemIntrinsic()
1208 Info.memVT = MVT::getVT(CI.getType()); in getTgtMemIntrinsic()
9411 VTSign->getVT() == MVT::i8) || in performSignExtendInRegCombine()
9413 VTSign->getVT() == MVT::i16)) && in performSignExtendInRegCombine()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td923 def vtInt : PatLeaf<(vt), [{ return N->getVT().isInteger(); }]>;
924 def vtFP : PatLeaf<(vt), [{ return N->getVT().isFloatingPoint(); }]>;
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h2222 EVT getVT() const { return ValueType; }
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp509 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT(); in performANDCombine()
917 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT(); in performSRACombine()

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