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Searched refs:getVGPRClassForBitWidth (Results 1 – 4 of 4) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.cpp1977 SIRegisterInfo::getVGPRClassForBitWidth(unsigned BitWidth) const { in getVGPRClassForBitWidth() function in SIRegisterInfo
2163 const TargetRegisterClass *VRC = getVGPRClassForBitWidth(Size); in hasVGPRs()
2177 assert(getVGPRClassForBitWidth(Size) && "Invalid register class size"); in hasAGPRs()
2186 const TargetRegisterClass *VRC = getVGPRClassForBitWidth(Size); in getEquivalentVGPRClass()
2224 RC = getVGPRClassForBitWidth(Size); in getSubRegClass()
2409 return getVGPRClassForBitWidth(std::max(32u, Size)); in getRegClassForSizeOnBank()
2536 return RC.hasSuperClassEq(getVGPRClassForBitWidth(getRegSizeInBits(RC))); in isProperlyAlignedRC()
H A DSIRegisterInfo.h141 const TargetRegisterClass *getVGPRClassForBitWidth(unsigned BitWidth) const;
H A DSIISelLowering.cpp94 addRegisterClass(MVT::v3f32, TRI->getVGPRClassForBitWidth(96)); in SITargetLowering()
100 addRegisterClass(MVT::v4f32, TRI->getVGPRClassForBitWidth(128)); in SITargetLowering()
103 addRegisterClass(MVT::v5f32, TRI->getVGPRClassForBitWidth(160)); in SITargetLowering()
106 addRegisterClass(MVT::v6f32, TRI->getVGPRClassForBitWidth(192)); in SITargetLowering()
109 addRegisterClass(MVT::v3f64, TRI->getVGPRClassForBitWidth(192)); in SITargetLowering()
112 addRegisterClass(MVT::v7f32, TRI->getVGPRClassForBitWidth(224)); in SITargetLowering()
115 addRegisterClass(MVT::v8f32, TRI->getVGPRClassForBitWidth(256)); in SITargetLowering()
118 addRegisterClass(MVT::v4f64, TRI->getVGPRClassForBitWidth(256)); in SITargetLowering()
121 addRegisterClass(MVT::v16f32, TRI->getVGPRClassForBitWidth(512)); in SITargetLowering()
124 addRegisterClass(MVT::v8f64, TRI->getVGPRClassForBitWidth(512)); in SITargetLowering()
[all …]
H A DSILoadStoreOptimizer.cpp1597 : TRI->getVGPRClassForBitWidth(BitWidth); in getTargetRegisterClass()