| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 2728 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, in LowerF64Op()
2730 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, in LowerF64Op()
2884 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128, in LowerFNEGorFABS()
2886 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128, in LowerFNEGorFABS()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 2600 Base = CurDAG->getTargetInsertSubreg(X86::sub_32bit, DL, MVT::i64, ImplDef, in selectLEA64_32Addr()
2612 Index = CurDAG->getTargetInsertSubreg(X86::sub_32bit, DL, MVT::i64, ImplDef, in selectLEA64_32Addr()
4472 Src0 = CurDAG->getTargetInsertSubreg(SubReg, dl, CmpVT, ImplDef, Src0); in tryVPTESTM()
4475 Src1 = CurDAG->getTargetInsertSubreg(SubReg, dl, CmpVT, ImplDef, Src1); in tryVPTESTM()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelDAGToDAG.cpp | 950 return CurDAG->getTargetInsertSubreg(SystemZ::subreg_l32, in convertTo()
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| H A D | SystemZISelLowering.cpp | 3395 In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL, in lowerBITCAST()
3408 SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL, in lowerBITCAST()
3707 return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL, in lowerOR()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 1307 SDValue Insert = CurDAG->getTargetInsertSubreg(SubRegIdx, DL, VT, V, SubV); in Select()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | SelectionDAG.h | 1470 SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT,
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelDAGToDAG.cpp | 3120 SDValue NewIns = CurDAG->getTargetInsertSubreg( in tryInsertVectorElt()
3140 CurDAG->getTargetInsertSubreg(ARM::ssub_0 + Lane2 / 2, dl, MVT::v4f32, in tryInsertVectorElt()
3152 CurDAG->getTargetInsertSubreg(ARM::ssub_0 + Lane2 / 2, dl, MVT::v4f32, in tryInsertVectorElt()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLoweringHVX.cpp | 1046 return DAG.getTargetInsertSubreg(SubIdx, dl, VecTy, VecV, SubV); in insertHvxSubvectorReg()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 1622 return DAG.getTargetInsertSubreg(AArch64::dsub, DL, WideTy, Undef, V64Reg); in operator ()()
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| H A D | AArch64ISelLowering.cpp | 7011 VecVal1 = DAG.getTargetInsertSubreg(Idx, DL, VecVT, in LowerFCOPYSIGN()
7013 VecVal2 = DAG.getTargetInsertSubreg(Idx, DL, VecVT, in LowerFCOPYSIGN()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 8713 SDValue SelectionDAG::getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT, in getTargetInsertSubreg() function in SelectionDAG
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