Searched refs:getSubRegFromChannel (Results 1 – 12 of 12) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | R600ExpandSpecialInstrs.cpp | 210 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction() 215 unsigned SubRegIndex0 = R600RegisterInfo::getSubRegFromChannel(CubeSrcSwz[Chan]); in runOnMachineFunction() 216 unsigned SubRegIndex1 = R600RegisterInfo::getSubRegFromChannel(CubeSrcSwz[3 - Chan]); in runOnMachineFunction() 225 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(Chan); in runOnMachineFunction()
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| H A D | R600RegisterInfo.h | 27 static unsigned getSubRegFromChannel(unsigned Channel);
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| H A D | R600RegisterInfo.cpp | 24 unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) { in getSubRegFromChannel() function in R600RegisterInfo
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| H A D | SIRegisterInfo.h | 55 static unsigned getSubRegFromChannel(unsigned Channel, unsigned NumRegs = 1);
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| H A D | R600ControlFlowFinalizer.cpp | 280 R600RegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)), in isCompatibleWithClause() 289 R600RegisterInfo::getSubRegFromChannel(TRI->getHWRegChan(Reg)), in isCompatibleWithClause()
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| H A D | SIShrinkInstructions.cpp | 430 Reg = TRI.getSubReg(Reg, TRI.getSubRegFromChannel(I)); in getSubRegForIndex() 432 Sub = TRI.getSubRegFromChannel(I + TRI.getChannelFromSubReg(Sub)); in getSubRegForIndex()
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| H A D | SIRegisterInfo.cpp | 427 unsigned SIRegisterInfo::getSubRegFromChannel(unsigned Channel, in getSubRegFromChannel() function in SIRegisterInfo 1165 getSubRegFromChannel(RegOffset / 4, NumRegs))); in buildSpillLoadStore() 1185 ? Register(getSubReg(ValueReg, getSubRegFromChannel(Lane))) in buildSpillLoadStore() 1216 getSubRegFromChannel(RemRegOffset / 4, NumRegs))); in buildSpillLoadStore()
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| H A D | AMDGPUISelDAGToDAG.cpp | 744 unsigned Sub = IsGCN ? SIRegisterInfo::getSubRegFromChannel(i) in SelectBuildVector() 745 : R600RegisterInfo::getSubRegFromChannel(i); in SelectBuildVector() 755 unsigned Sub = IsGCN ? SIRegisterInfo::getSubRegFromChannel(i) in SelectBuildVector() 756 : R600RegisterInfo::getSubRegFromChannel(i); in SelectBuildVector()
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| H A D | SIInstrInfo.cpp | 627 SubIdx = RI.getSubRegFromChannel(Channel, 2); in expandSGPRCopy() 5019 .addReg(SrcReg, 0, RI.getSubRegFromChannel(i)); in readlaneVGPRToSGPR() 5028 MIB.addImm(RI.getSubRegFromChannel(i)); in readlaneVGPRToSGPR() 5232 .addReg(VRsrc, VRsrcUndef, TRI->getSubRegFromChannel(Idx)); in emitLoadSRsrcFromVGPRLoop() 5236 .addReg(VRsrc, VRsrcUndef, TRI->getSubRegFromChannel(Idx + 1)); in emitLoadSRsrcFromVGPRLoop() 5256 Cmp.addReg(VRsrc, VRsrcUndef, TRI->getSubRegFromChannel(Idx, 2)); in emitLoadSRsrcFromVGPRLoop() 5278 .addImm(TRI->getSubRegFromChannel(Channel++)); in emitLoadSRsrcFromVGPRLoop()
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| H A D | R600InstrInfo.cpp | 57 unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(I); in copyPhysReg()
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| H A D | AMDGPUInstructionSelector.cpp | 487 unsigned SubReg = SIRegisterInfo::getSubRegFromChannel(Offset / 32, in selectG_EXTRACT() 720 unsigned SubReg = TRI.getSubRegFromChannel(Offset / 32, InsSize / 32); in selectG_INSERT()
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| H A D | SIISelLowering.cpp | 3688 return std::make_pair(SIRegisterInfo::getSubRegFromChannel(Offset), 0); in computeIndirectRegAndOffset() 11301 .addImm(SIRegisterInfo::getSubRegFromChannel(CurrIdx)); in AddIMGInit()
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