Home
last modified time | relevance | path

Searched refs:getSubRegClass (Results 1 – 6 of 6) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h196 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
H A DSIFixSGPRCopies.cpp272 SrcRC = TRI->getSubRegClass(SrcRC, SrcSubReg); in foldVGPRCopyIntoRegSequence()
H A DSIInstrInfo.cpp3864 RI.getSubRegClass(RC, MO.getSubReg()); in verifyInstruction()
6409 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
6416 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitUnaryOp()
6473 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitAddSub()
6474 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitAddSub()
6539 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
6544 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
6557 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0); in splitScalar64BitBinaryOp()
6646 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0); in splitScalar64BitBCNT()
H A DSIWholeQuadMode.cpp1434 regClass = TRI->getSubRegClass(regClass, SubReg); in lowerCopyInstrs()
H A DSIRegisterInfo.cpp2209 const TargetRegisterClass *SIRegisterInfo::getSubRegClass( in getSubRegClass() function in SIRegisterInfo
H A DSIISelLowering.cpp4016 TRI->getSubRegClass(Src0RC, AMDGPU::sub0); in EmitInstrWithCustomInserter()
4018 TRI->getSubRegClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter()
4101 TRI->getSubRegClass(Src2RC, AMDGPU::sub0); in EmitInstrWithCustomInserter()