| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreMachineFunctionInfo.cpp | 46 TRI.getSpillAlign(RC), true); in createLRSpillSlot() 60 MFI.CreateStackObject(TRI.getSpillSize(RC), TRI.getSpillAlign(RC), true); in createFPSpillSlot() 73 Align Alignment = TRI.getSpillAlign(RC); in createEHSpillSlot()
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| H A D | XCoreFrameLowering.cpp | 578 Align Alignment = TRI.getSpillAlign(RC); in processFunctionBeforeFrameFinalized()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsMachineFunction.cpp | 158 TRI.getSpillSize(RC), TRI.getSpillAlign(RC), false); in createEhDataRegsFI() 172 TRI.getSpillSize(RC), TRI.getSpillAlign(RC), false); in createISRRegFI() 198 TRI.getSpillSize(*RC), TRI.getSpillAlign(*RC), false); in getMoveF64ViaSpillFI()
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| H A D | MipsSEFrameLowering.cpp | 897 TRI->getSpillAlign(RC), false); in determineCalleeSaves() 913 TRI->getSpillAlign(RC), false); in determineCalleeSaves()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86LowerTileCopy.cpp | 93 Align Alignment = TRI->getSpillAlign(X86::TILERegClass); in runOnMachineFunction() 97 Alignment = TRI->getSpillAlign(X86::GR64RegClass); in runOnMachineFunction()
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| H A D | X86FrameLowering.cpp | 2504 Align Alignment = TRI->getSpillAlign(*RC); in assignCalleeSavedSpillSlots()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPreAllocateWWMRegs.cpp | 161 TRI->getSpillAlign(*RC)); in rewriteRegs()
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| H A D | SILowerSGPRSpills.cpp | 220 TRI->getSpillAlign(*RC), true); in spillCalleeSavedRegs()
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| H A D | SIMachineFunctionInfo.cpp | 479 TRI.getSpillAlign(AMDGPU::SGPR_32RegClass), false); in getScavengeFI()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonVExtract.cpp | 140 Align Alignment = HRI.getSpillAlign(VecRC); in runOnMachineFunction()
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| H A D | HexagonFrameLowering.cpp | 1715 Align Alignment = std::min(TRI->getSpillAlign(*RC), getStackAlign()); in assignCalleeSavedSpillSlots() 1939 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandStoreVec2() 1991 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandLoadVec2() 2035 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandStoreVec() 2065 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandLoadVec() 2169 Align A = HRI.getSpillAlign(*RC); in determineCalleeSaves()
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| H A D | HexagonInstrInfo.cpp | 1089 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() 1105 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() 1127 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() 1144 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo()
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| H A D | HexagonISelLowering.cpp | 527 Align VecAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in LowerCall()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVFrameLowering.cpp | 895 RegInfo->getSpillAlign(*RC), false); in processFunctionBeforeFrameFinalized() 901 RegInfo->getSpillSize(*RC), RegInfo->getSpillAlign(*RC), false); in processFunctionBeforeFrameFinalized()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 286 Align getSpillAlign(const TargetRegisterClass &RC) const { in getSpillAlign() function
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCFrameLowering.cpp | 443 RegInfo->getSpillAlign(*RC), false); in processFunctionBeforeFrameFinalized()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | VirtRegMap.cpp | 97 Align Alignment = TRI->getSpillAlign(*RC); in createSpillSlot()
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| H A D | RegisterScavenging.cpp | 455 Align NeedAlign = TRI->getSpillAlign(RC); in spill()
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| H A D | PrologEpilogInserter.cpp | 446 Align Alignment = RegInfo->getSpillAlign(*RC); in assignCalleeSavedSpillSlots()
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| H A D | RegAllocFast.cpp | 332 Align Alignment = TRI->getSpillAlign(RC); in getStackSpaceFor()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64FrameLowering.cpp | 2874 Align Alignment = TRI->getSpillAlign(RC); in determineCalleeSaves() 2931 Align Alignment(RegInfo->getSpillAlign(*RC)); in assignCalleeSavedSpillSlots()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFrameLowering.cpp | 2283 Align Alignment = TRI->getSpillAlign(RC); in determineCalleeSaves()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFrameLowering.cpp | 2288 Align Alignment = TRI.getSpillAlign(RC); in addScavengingSpillSlot()
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