Searched refs:getShiftValue (Results 1 – 11 of 11) sorted by relevance
274 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()553 unsigned ShiftVal = AArch64_AM::getShiftValue(ShiftOpnd); in getImm8OptLsl()580 unsigned ShiftVal = AArch64_AM::getShiftValue(MO.getImm()); in getMoveVecShifterOpValue()
1027 AArch64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm()); in printAddSubImm()1056 AArch64_AM::getShiftValue(Val) == 0) in printShifter()1059 << " #" << AArch64_AM::getShiftValue(Val); in printShifter()1681 if ((UnscaledVal == 0) && (AArch64_AM::getShiftValue(Shift) != 0)) { in printImm8OptLsl()1689 Val = (int8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift)); in printImm8OptLsl()1691 Val = (uint8_t)UnscaledVal * (1 << AArch64_AM::getShiftValue(Shift)); in printImm8OptLsl()
85 static inline unsigned getShiftValue(unsigned Imm) { in getShiftValue() function
175 unsigned ShiftAmt = AArch64_AM::getShiftValue(I.getOperand(3).getImm()); in findSuitableCompare()
57 let FunctionMapper = "AArch64_AM::getShiftValue" in
1779 assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 && in mergeUpdateInsn()1846 if (AArch64_AM::getShiftValue(MI.getOperand(3).getImm())) in isMatchingUpdateInsn()
1331 Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0))); in emitInstruction()
895 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast()922 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast()930 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm); in isFalkorShiftExtFast()
2246 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); in getUsefulBitsFromOrWithShiftedReg()2254 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue); in getUsefulBitsFromOrWithShiftedReg()
3272 unsigned Shift = AArch64_AM::getShiftValue(MI.getOperand(3).getImm()); in canMergeRegUpdate()
2258 OS << ", lsl #" << AArch64_AM::getShiftValue(Shift) << ">"; in print()