Searched refs:getRegClassForTypeOnBank (Results 1 – 5 of 5) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 49 getRegClassForTypeOnBank(Register Reg, MachineRegisterInfo &MRI) const;
111 const TargetRegisterClass *RC = getRegClassForTypeOnBank(DstReg, MRI); in selectCopy()
120 const TargetRegisterClass *MipsInstructionSelector::getRegClassForTypeOnBank( in getRegClassForTypeOnBank() function in MipsInstructionSelector
433 DefRC = getRegClassForTypeOnBank(DestReg, MRI); in select()
580 MRI.setRegClass(Dst, getRegClassForTypeOnBank(Dst, MRI)); in select()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 268 getRegClassForTypeOnBank(LLT Ty, in getRegClassForTypeOnBank() function
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| H A D | AMDGPUInstructionSelector.cpp | 219 DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB, *MRI); in selectPHI()
2039 TRI.getRegClassForTypeOnBank(SrcTy, *SrcBank, *MRI); in selectG_SZA_EXT()
2544 const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB, in selectG_PTRMASK()
2546 const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(Ty, *SrcRB, in selectG_PTRMASK()
2549 TRI.getRegClassForTypeOnBank(MaskTy, *MaskRB, *MRI); in selectG_PTRMASK()
2670 const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(SrcTy, *SrcRB, in selectG_EXTRACT_VECTOR_ELT()
2672 const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(DstTy, *DstRB, in selectG_EXTRACT_VECTOR_ELT()
2752 const TargetRegisterClass *VecRC = TRI.getRegClassForTypeOnBank(VecTy, *VecRB, in selectG_INSERT_VECTOR_ELT()
2754 const TargetRegisterClass *ValRC = TRI.getRegClassForTypeOnBank(ValTy, *ValRB, in selectG_INSERT_VECTOR_ELT()
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| H A D | SIRegisterInfo.cpp | 2428 return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB, MRI); in getConstrainedRegClassForOperand()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 483 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB, in getRegClassForTypeOnBank() function
1801 getRegClassForTypeOnBank(Ty, RBI.getRegBank(AArch64::FPRRegBankID), RBI); in selectVectorAshrLshr()
2307 DefRC = getRegClassForTypeOnBank(DefTy, RB, RBI); in select()
2949 getRegClassForTypeOnBank(DstTy, DstRB, RBI); in select()
2954 getRegClassForTypeOnBank(SrcTy, SrcRB, RBI); in select()
3272 getRegClassForTypeOnBank(DstTy, DstRB, RBI); in select()
3721 getRegClassForTypeOnBank(SrcTy, VecRB, RBI, true); in selectVectorICmp()
3883 getRegClassForTypeOnBank(ScalarTy, DstRB, RBI, true); in emitExtractVectorElt()
3892 getRegClassForTypeOnBank(VecTy, VecRB, RBI, true); in emitExtractVectorElt()
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