Searched refs:getPhysRegClass (Results 1 – 9 of 9) sorted by relevance
159 const TargetRegisterClass *RC = TRI->getPhysRegClass(PhysReg); in rewriteRegs()
151 const TargetRegisterClass *getPhysRegClass(MCRegister Reg) const;
149 : TRI.getPhysRegClass(SrcReg); in getCopyRegClasses()156 : TRI.getPhysRegClass(DstReg); in getCopyRegClasses()
118 const TargetRegisterClass *RC = TRI.getPhysRegClass(SuperReg); in SGPRSpillBuilder()2077 SIRegisterInfo::getPhysRegClass(MCRegister Reg) const { in getPhysRegClass() function in SIRegisterInfo2151 RC = getPhysRegClass(Reg); in isSGPRReg()2317 return Reg.isVirtual() ? MRI.getRegClass(Reg) : getPhysRegClass(Reg); in getRegClassForReg()2515 assert(getRegSizeInBits(*getPhysRegClass(Reg)) <= 32); in get32BitRegister()
583 TRI->hasVectorRegisters(TRI->getPhysRegClass(Reg))) { in scanInstructions()1432 Reg.isVirtual() ? MRI->getRegClass(Reg) : TRI->getPhysRegClass(Reg); in lowerCopyInstrs()
981 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) { in fixSMEMtoVectorWriteHazards()1062 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) in fixVcmpxExecWARHazard()
658 const TargetRegisterClass *RC = RI.getPhysRegClass(DestReg); in copyPhysReg()664 (RI.getRegSizeInBits(*RI.getPhysRegClass(SrcReg)) == 16))) { in copyPhysReg()676 RC = RI.getPhysRegClass(DestReg); in copyPhysReg()865 const TargetRegisterClass *SrcRC = RI.getPhysRegClass(SrcReg); in copyPhysReg()2908 RI.isSGPRClass(RI.getPhysRegClass(Src0->getReg())))) || in FoldImmediate()2925 RI.isSGPRClass(RI.getPhysRegClass(Src1->getReg()))) || in FoldImmediate()4563 return RI.getPhysRegClass(Reg); in getOpRegClass()
937 RC = TRI->getPhysRegClass(AssignedReg); in isInlineAsmSourceOfDivergence()
630 return TRI->getPhysRegClass(Reg); in getOperandRegClass()1649 TRI.getPhysRegClass(cast<RegisterSDNode>(Val.getOperand(1))->getReg()); in IsCopyFromSGPR()