Searched refs:getIssueWidth (Results 1 – 9 of 9) sorted by relevance
50 unsigned InOrderIssueStage::getIssueWidth() const { in getIssueWidth() function in llvm::mca::InOrderIssueStage66 bool ShouldCarryOver = NumMicroOps > getIssueWidth(); in isAvailable()363 Bandwidth = getIssueWidth(); in cycleStart()398 assert((NumIssued <= getIssueWidth()) && "Overflow."); in cycleStart()
59 Packet.resize(SchedModel->getIssueWidth()); in VLIWResourceModel()175 CriticalPathLength = DAG->getBBSize() / SchedModel->getIssueWidth(); in init()
150 Packet.size() >= SchedModel->getIssueWidth()) { in reserveResources()341 if (IssueCount + uops > SchedModel->getIssueWidth()) in checkHazard()363 unsigned Width = SchedModel->getIssueWidth(); in bumpCycle()
115 unsigned getIssueWidth() const;
99 unsigned getIssueWidth() const { return SchedModel.IssueWidth; } in getIssueWidth() function
226 unsigned IssueWidth = TSM.getIssueWidth(); in addPadding()
1218 if (unsigned IW = TE.MTM.SchedModel.getIssueWidth()) in getResourceDepth()1272 if (unsigned IW = TE.MTM.SchedModel.getIssueWidth()) in getResourceLength()
2172 if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) { in checkHazard()2301 unsigned DecMOps = SchedModel->getIssueWidth() * (NextCycle - CurrCycle); in bumpCycle()2395 (CurrMOps == 0 || (CurrMOps + IncMOps) <= SchedModel->getIssueWidth()) && in bumpNode()2513 while (CurrMOps >= SchedModel->getIssueWidth()) { in bumpNode()
731 if (Metrics.NumInsts <= (6 * SchedModel.getIssueWidth())) in isHardwareLoopProfitable()