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Searched refs:getDesc (Results 1 – 25 of 151) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h341 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
349 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
365 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
479 return MI.getDesc().TSFlags & SIInstrFlags::DS; in isDS()
511 auto Flags = MI.getDesc().TSFlags; in isSegmentSpecificFLAT()
542 return MI.getDesc().TSFlags & SIInstrFlags::EXP; in isEXP()
576 return MI.getDesc().TSFlags & SIInstrFlags::WQM; in isWQM()
608 return MI.getDesc().TSFlags & SIInstrFlags::DPP; in isDPP()
710 return MI.getDesc().TSFlags & ClampFlags; in getClampMask()
775 if (!MI.getDesc().OpInfo || OpIdx >= MI.getDesc().NumOperands) { in isInlineConstant()
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H A DSIPostRABundler.cpp107 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags; in isBundleCandidate()
113 const uint64_t IMemFlags = MI.getDesc().TSFlags & MemFlags; in canBundle()
117 ((NextMI.getDesc().TSFlags & MemFlags) == IMemFlags) && in canBundle()
H A DSIShrinkInstructions.cpp161 for (unsigned i = MI.getDesc().getNumOperands() + in copyExtraImplicitOps()
162 MI.getDesc().getNumImplicitUses() + in copyExtraImplicitOps()
163 MI.getDesc().getNumImplicitDefs(), e = MI.getNumOperands(); in copyExtraImplicitOps()
440 for (unsigned i = MI.getDesc().getNumOperands() + in dropInstructionKeepingImpDefs()
441 MI.getDesc().getNumImplicitUses() + in dropInstructionKeepingImpDefs()
442 MI.getDesc().getNumImplicitDefs(), e = MI.getNumOperands(); in dropInstructionKeepingImpDefs()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp236 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
243 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
311 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
329 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
335 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
341 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
374 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
551 HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) || in isConstExtended()
553 HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch())) in isConstExtended()
573 return !HexagonMCInstrInfo::getDesc(MCII, MCI).isPseudo() && in isCanon()
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H A DHexagonShuffler.cpp130 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
197 MCInst const &Inst = ISJ.getDesc(); in restrictSlot1AOK()
229 MCInst const &Inst = ISJ.getDesc(); in restrictNoSlot1Store()
230 if (HexagonMCInstrInfo::getDesc(MCII, Inst).mayStore()) { in restrictNoSlot1Store()
364 MCInst const &ID = ISJ->getDesc(); in restrictStoreLoadOrder()
371 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { in restrictStoreLoadOrder()
404 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayStore()) { in restrictStoreLoadOrder()
446 MCInst const &ID = ISJ->getDesc(); in GetPacketSummary()
485 if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn()) in GetPacketSummary()
533 if (HexagonMCInstrInfo::getDesc(MCII, ID).isBranch()) in GetPacketSummary()
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H A DHexagonMCChecker.cpp90 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init()
312 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in reportBranchErrors()
323 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in checkHWLoop()
337 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in checkCOFMax1()
425 bool Branch = HexagonMCInstrInfo::getDesc(MCII, I).isBranch(); in checkNewValues()
465 HexagonMCInstrInfo::getDesc(MCII, *std::get<0>(Producer)); in checkNewValues()
506 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); in checkRegistersReadOnly()
523 for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(), in registerUsed()
539 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in registerProducer()
564 HexagonMCInstrInfo::getDesc(MCII, I).mayLoad()) { in checkRegisterCurDefs()
H A DHexagonMCShuffler.cpp41 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); in init()
63 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
86 MCInst const &MI = I->getDesc(); in copyTo()
/freebsd-13.1/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DSchedulerStatistics.cpp47 NumIssued += Inst.getDesc().NumMicroOps; in onEvent()
51 if (LQResourceID && Inst.getDesc().MayLoad && in onEvent()
56 if (SQResourceID && Inst.getDesc().MayStore && in onEvent()
63 if (LQResourceID && Inst.getDesc().MayLoad) { in onEvent()
67 if (SQResourceID && Inst.getDesc().MayStore) { in onEvent()
/freebsd-13.1/contrib/llvm-project/llvm/lib/MCA/Stages/
H A DInOrderIssueStage.cpp64 const InstrDesc &Desc = Inst.getDesc(); in isAvailable()
79 if (RM.checkAvailability(IR.getInstruction()->getDesc())) { in hasResourceHazard()
134 if (!IR.getInstruction()->getDesc().RetireOOO) { in canExecute()
203 const InstrDesc &Desc = IS.getDesc(); in tryIssue()
258 if (!IR.getInstruction()->getDesc().RetireOOO) in tryIssue()
310 if (CarriedOver.getInstruction()->getDesc().EndGroup) in updateCarriedOver()
H A DDispatchStage.cpp81 const InstrDesc &Desc = IS.getDesc(); in dispatch()
162 const InstrDesc &Desc = Inst.getDesc(); in isAvailable()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp110 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
135 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass()
198 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
242 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
327 unsigned SchedClass = MI->getDesc().getSchedClass(); in computeReciprocalThroughput()
H A DExecutionDomainFix.cpp237 const MCInstrDesc &MCID = MI->getDesc(); in processDefs()
259 for (unsigned i = mi->getDesc().getNumDefs(), in visitHardInstr()
260 e = mi->getDesc().getNumOperands(); in visitHardInstr()
271 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitHardInstr()
290 for (unsigned i = mi->getDesc().getNumDefs(), in visitSoftInstr()
291 e = mi->getDesc().getNumOperands(); in visitSoftInstr()
H A DTargetInstrInfo.cpp170 const MCInstrDesc &MCID = MI.getDesc(); in commuteInstructionImpl()
207 MI.getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
212 MI.getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { in commuteInstructionImpl()
302 const MCInstrDesc &MCID = MI.getDesc(); in findCommutedOpIndices()
338 const MCInstrDesc &MCID = MI.getDesc(); in PredicateInstruction()
1125 unsigned Class = MI.getDesc().getSchedClass(); in getNumMicroOps()
1159 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrLatency()
1169 unsigned DefClass = DefMI.getDesc().getSchedClass(); in hasLowDefLatency()
1262 unsigned DefClass = DefMI.getDesc().getSchedClass(); in getOperandLatency()
1263 unsigned UseClass = UseMI.getDesc().getSchedClass(); in getOperandLatency()
H A DPeepholeOptimizer.cpp890 NumDefs = MI.getDesc().getNumDefs(); in UncoalescableRewriter()
1190 assert(MI.getDesc().getNumDefs() == 1 && in optimizeCoalescableCopy()
1336 const MCInstrDesc &MCID = MI.getDesc(); in isLoadFoldable()
1355 const MCInstrDesc &MCID = MI.getDesc(); in isMoveImmediate()
1376 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) { in foldImmediate()
1531 if (MI.getDesc().getNumDefs() != 1) in findTargetRecurrence()
1770 const MCInstrDesc &MIDesc = MI->getDesc(); in runOnMachineFunction()
1852 if (Def->getDesc().getNumDefs() != 1) in getNextSourceFromBitcast()
2068 (DefIdx < Def->getDesc().getNumDefs() || in getNextSourceImpl()
2069 Def->getDesc().isVariadic())) || in getNextSourceImpl()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86DiscriminateMemOps.cpp113 if (BypassPrefetchInstructions && IsPrefetchOpcode(MI.getDesc().Opcode)) in runOnMachineFunction()
129 if (X86II::getMemoryOperandNo(MI.getDesc().TSFlags) < 0) in runOnMachineFunction()
131 if (BypassPrefetchInstructions && IsPrefetchOpcode(MI.getDesc().Opcode)) in runOnMachineFunction()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMHazardRecognizer.cpp29 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
50 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
53 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
110 uint64_t TSFlags = MI.getDesc().TSFlags; in getBaseOffset()
H A DARMBaseRegisterInfo.cpp519 const MCInstrDesc &Desc = MI->getDesc(); in getFrameIndexInstrOffset()
709 const MCInstrDesc &Desc = MI->getDesc(); in isFrameOffsetLegal()
823 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 || in eliminateFrameIndex()
824 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6 || in eliminateFrameIndex()
825 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7 || in eliminateFrameIndex()
826 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrModeT2_i7s2 || in eliminateFrameIndex()
827 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == in eliminateFrameIndex()
837 const MCInstrDesc &MCID = MI.getDesc(); in eliminateFrameIndex()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrBuilder.h63 const MCInstrDesc &MCID = MI->getDesc();
80 const MCInstrDesc &MCID = MI->getDesc();
/freebsd-13.1/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp74 const InstrDesc &D = IS->getDesc(); in issueInstructionImpl()
199 uint64_t BusyResourceMask = Resources->checkAvailability(IS.getDesc()); in select()
253 if (Resources->checkAvailability(IS.getDesc())) in analyzeDataDependencies()
291 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in mustIssueImmediately()
H A DLSUnit.cpp70 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in dispatch()
196 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in isAvailable()
214 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in onInstructionRetired()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Support/
H A DStatistic.cpp149 return std::strcmp(LHS->getDesc(), RHS->getDesc()) < 0; in sort()
199 Stats.Stats[i]->getDesc()); in PrintStatistics()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp1581 const uint64_t F = MI.getDesc().TSFlags; in isPredicated()
1671 if (!MI.getDesc().isPredicable()) in isPredicable()
2035 const uint64_t F = MI.getDesc().TSFlags; in isAccumulator()
2045 !MI.getDesc().mayStore() && in isComplex()
2059 const uint64_t F = MI.getDesc().TSFlags; in isConstExtended()
2118 if (!ProdMI.getDesc().getNumDefs()) in isDependent()
2206 const MCInstrDesc &MID = MI.getDesc(); in isExtendable()
2229 const uint64_t F = MI.getDesc().TSFlags; in isExtended()
3032 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) { in hasNonExtEquivalent()
4424 if (MI.getDesc().mayLoad() || MI.getDesc().mayStore()) { in getNonExtOpcode()
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H A DHexagonOptAddrMode.cpp127 const MCInstrDesc &MID = MI.getDesc(); in INITIALIZE_PASS_DEPENDENCY()
194 const MCInstrDesc &UseMID = UseMI.getDesc(); in canRemoveAddasl()
357 const MCInstrDesc &MID = MI->getDesc(); in processAddUses()
416 const MCInstrDesc &MID = UseMI->getDesc(); in updateAddUses()
444 const MCInstrDesc &MID = MI.getDesc(); in analyzeUses()
626 const MCInstrDesc &UseMID = UseMI->getDesc(); in changeAddAsl()
673 const MCInstrDesc &MID = UseMI->getDesc(); in xformUseMI()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp478 assert(LastInst.getDesc().isConditionalBranch() && in parseCondBranch()
525 if (J->getDesc().isUnconditionalBranch() || in analyzeBranch()
526 J->getDesc().isIndirectBranch()) { in analyzeBranch()
542 if (I->getDesc().isIndirectBranch()) in analyzeBranch()
563 I->getDesc().isUnconditionalBranch()) { in analyzeBranch()
581 if (!I->getDesc().isUnconditionalBranch() && in removeBranch()
582 !I->getDesc().isConditionalBranch()) in removeBranch()
595 if (!I->getDesc().isConditionalBranch()) in removeBranch()
689 assert(MI.getDesc().isBranch() && "Unexpected opcode!"); in getBranchDestBlock()
1084 MI.getDesc().hasImplicitDefOfPhysReg(RISCV::X5)) in getOutliningType()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstrInfo.cpp568 return (MI.getDesc().TSFlags & MipsII::IsCTI) == 0; in SafeInForbiddenSlot()
573 return (MI.getDesc().TSFlags & MipsII::HasForbiddenSlot) != 0; in HasForbiddenSlot()
580 return MI.getDesc().getSize(); in getInstSizeInBytes()
651 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) { in genInstrWithNewOpc()
659 for (unsigned J = I->getDesc().getNumOperands(), E = I->getNumOperands(); in genInstrWithNewOpc()
668 for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) { in genInstrWithNewOpc()
687 const MCInstrDesc &MCID = MI.getDesc(); in findCommutedOpIndices()

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