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Searched refs:getCondCode (Results 1 – 17 of 17) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp324 static MSP430CC::CondCodes getCondCode(unsigned Cond) { in getCondCode() function
353 MI.addOperand(MCOperand::createImm(getCondCode(Cond))); in getInstructionCJ()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp800 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_UINT()
810 DAG.getCondCode(ISD::SETEQ)); in lowerFP_TO_SINT()
890 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC()
896 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC()
924 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
932 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
964 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC()
990 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
H A DSIISelLowering.cpp4772 DAG.getCondCode(CCOpcode)); in lowerICMPIntrinsic()
4802 Src1, DAG.getCondCode(CCOpcode)); in lowerFCMPIntrinsic()
4842 DAG.getConstant(0, SL, MVT::i32), DAG.getCondCode(ISD::SETNE)); in lowerBALLOTIntrinsic()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h778 SDValue getCondCode(ISD::CondCode Cond);
1069 {VT, MVT::Other}, {Chain, LHS, RHS, getCondCode(Cond)});
1070 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
1090 False, getCondCode(Cond));
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp919 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC()
1004 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC()
1026 NewRHS, DAG.getCondCode(CCCode)); in SoftenFloatOp_SETCC()
1029 DAG.getCondCode(CCCode)), 0); in SoftenFloatOp_SETCC()
1861 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC()
1946 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
H A DLegalizeIntegerTypes.cpp4367 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
4423 DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
4452 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC()
4471 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC()
4488 DAG.UpdateNodeOperands(N, NewLHS, NewRHS, DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
H A DLegalizeDAG.cpp3552 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
3683 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
3715 Tmp4 = DAG.getCondCode(NeedInvert ? ISD::SETEQ : ISD::SETNE); in ExpandNode()
H A DTargetLowering.cpp8851 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
8864 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
H A DSelectionDAG.cpp1738 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode() function in SelectionDAG
H A DSelectionDAGBuilder.cpp7305 Opers.push_back(DAG.getCondCode(Condition)); in visitConstrainedFPIntrinsic()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp944 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anon296d71d40111::ARMOperand
2419 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeNoAL()
2426 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedI()
2433 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedS()
2441 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedU()
2448 ARMCC::CondCodes CC = getCondCode(); in isITCondCodeRestrictedFP()
2475 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
2476 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
2526 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
3898 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; in print()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2964 SDValue TargetCC = DAG.getCondCode(CCVal); in lowerBRCOND()
2971 DAG.getCondCode(ISD::SETNE), Op.getOperand(2)); in lowerBRCOND()
3327 DAG.getCondCode(ISD::SETNE), Mask, VL); in lowerVectorMaskTrunc()
3638 DAG.getCondCode(ISD::SETEQ), Mask, VL); in LowerINTRINSIC_WO_CHAIN()
6186 N->getOperand(0), LHS, RHS, DAG.getCondCode(CCVal), in PerformDAGCombine()
6204 SDValue TargetCC = DAG.getCondCode(CCVal); in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp586 AArch64CC::CondCode getCondCode() const { in getCondCode() function in __anon56f6c4660111::AArch64Operand
1717 Inst.addOperand(MCOperand::createImm(getCondCode())); in addCondCodeOperands()
2262 OS << "<condcode " << getCondCode() << ">"; in print()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp14197 N->getOperand(2), Splat, DAG.getCondCode(CC)); in tryConvertSVEWideCompare()
14479 N->getOperand(3), DAG.getCondCode(ISD::SETUGE)); in performIntrinsicCombine()
14485 N->getOperand(3), DAG.getCondCode(ISD::SETUGT)); in performIntrinsicCombine()
14491 N->getOperand(3), DAG.getCondCode(ISD::SETGE)); in performIntrinsicCombine()
14497 N->getOperand(3), DAG.getCondCode(ISD::SETGT)); in performIntrinsicCombine()
14503 N->getOperand(3), DAG.getCondCode(ISD::SETEQ)); in performIntrinsicCombine()
14509 N->getOperand(3), DAG.getCondCode(ISD::SETNE)); in performIntrinsicCombine()
14514 N->getOperand(3), DAG.getCondCode(ISD::SETUO)); in performIntrinsicCombine()
15905 SetCC.getOperand(2) == DAG.getCondCode(ISD::SETGT)) { in performVSelectCombine()
17965 {Pg, Op1, Op2, DAG.getCondCode(ISD::SETNE)}); in convertFixedMaskToScalableVector()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp6619 DAG.getCondCode(ISD::SETEQ)); in LowerVSETCC()
8951 DAG.getCondCode(ISD::SETNE)); in LowerTruncatei1()
10094 DAG.getCondCode(CC)); in LowerFSETCC()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp3467 DAG.getCondCode(CC)); in LowerSETCC()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp22902 SDValue CC = DAG.getCondCode(Cond); in splitIntVSETCC()