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Searched refs:getBasePtr (Results 1 – 25 of 51) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGAddressAnalysis.cpp180 SDValue Ptr = N->getBasePtr(); in matchLSNode()
232 Base = DAG.getTargetLoweringInfo().unwrapAddress(LSBase->getBasePtr()); in matchLSNode()
H A DDAGCombiner.cpp15239 Ptr = LD->getBasePtr(); in getCombineLoadStoreParts()
15246 Ptr = ST->getBasePtr(); in getCombineLoadStoreParts()
15255 Ptr = LD->getBasePtr(); in getCombineLoadStoreParts()
15264 Ptr = ST->getBasePtr(); in getCombineLoadStoreParts()
15837 SDValue Ptr = LD->getBasePtr(); in visitLOAD()
16622 SDValue Ptr = St->getBasePtr(); in ShrinkLoadReplaceStoreWithStore()
16649 SDValue Ptr = ST->getBasePtr(); in ReduceLoadOpStoreWidth()
16689 if (LD->getBasePtr() != Ptr || in ReduceLoadOpStoreWidth()
17932 SDValue Ptr = ST->getBasePtr(); in replaceStoreOfFPConstant()
18342 SDValue Ptr = ST->getBasePtr(); in splitMergedValStore()
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H A DLegalizeVectorTypes.cpp362 N->getBasePtr(), DAG.getUNDEF(N->getBasePtr().getValueType()), in ScalarizeVecRes_LOAD()
1694 SDValue Ptr = LD->getBasePtr(); in SplitVecRes_LOAD()
1739 SDValue Ptr = MLD->getBasePtr(); in SplitVecRes_MLOAD()
1823 SDValue Ptr = MGT->getBasePtr(); in SplitVecRes_MGATHER()
2516 SDValue Ptr = MGT->getBasePtr(); in SplitVecOp_MGATHER()
2579 SDValue Ptr = N->getBasePtr(); in SplitVecOp_MSTORE()
2659 SDValue Ptr = N->getBasePtr(); in SplitVecOp_MSCATTER()
2723 SDValue Ptr = N->getBasePtr(); in SplitVecOp_STORE()
5260 SDValue BasePtr = LD->getBasePtr(); in GenWidenVectorLoads()
5412 SDValue BasePtr = LD->getBasePtr(); in GenWidenVectorExtLoads()
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H A DLegalizeFloatTypes.cpp696 L->getChain(), L->getBasePtr(), L->getOffset(), in SoftenFloatRes_LOAD()
707 dl, L->getChain(), L->getBasePtr(), L->getOffset(), in SoftenFloatRes_LOAD()
1058 return DAG.getStore(ST->getChain(), dl, Val, ST->getBasePtr(), in SoftenFloatOp_STORE()
1620 SDValue Ptr = LD->getBasePtr(); in ExpandFloatRes_LOAD()
1980 SDValue Ptr = ST->getBasePtr(); in ExpandFloatOp_STORE()
2193 return DAG.getStore(ST->getChain(), DL, NewVal, ST->getBasePtr(), in PromoteFloatOp_STORE()
2469 L->getChain(), L->getBasePtr(), L->getOffset(), L->getPointerInfo(), IVT, in PromoteFloatRes_LOAD()
2544 { AM->getChain(), AM->getBasePtr(), CastVal }, in BitcastToInt_ATOMIC_SWAP()
2774 SDLoc(N), L->getChain(), L->getBasePtr(), L->getOffset(), in SoftPromoteHalfRes_LOAD()
3017 return DAG.getStore(ST->getChain(), dl, Promoted, ST->getBasePtr(), in SoftPromoteHalfOp_STORE()
H A DLegalizeTypesGeneric.cpp259 SDValue Ptr = LD->getBasePtr(); in ExpandRes_NormalLoad()
469 SDValue Ptr = St->getBasePtr(); in ExpandOp_NormalStore()
H A DStatepointLowering.cpp572 LPadPointers.insert(Builder.getValue(Relocate->getBasePtr())); in lowerStatepointMetaArgs()
1043 SI.Bases.push_back(Relocate->getBasePtr()); in LowerStatepoint()
H A DLegalizeIntegerTypes.cpp267 N->getChain(), N->getBasePtr(), in PromoteIntRes_Atomic0()
279 N->getChain(), N->getBasePtr(), in PromoteIntRes_Atomic1()
302 N->getChain(), N->getBasePtr(), N->getOperand(2), N->getOperand(3), in PromoteIntRes_AtomicCmpSwap()
331 N->getBasePtr(), Op2, Op3, N->getMemOperand()); in PromoteIntRes_AtomicCmpSwap()
692 SDValue Res = DAG.getExtLoad(ExtType, dl, NVT, N->getChain(), N->getBasePtr(), in PromoteIntRes_LOAD()
706 SDValue Res = DAG.getMaskedLoad(NVT, dl, N->getChain(), N->getBasePtr(), in PromoteIntRes_MLOAD()
727 SDValue Ops[] = {N->getChain(), ExtPassThru, N->getMask(), N->getBasePtr(), in PromoteIntRes_MGATHER()
1823 SDValue Ch = N->getChain(), Ptr = N->getBasePtr(); in PromoteIntOp_STORE()
1854 return DAG.getMaskedStore(N->getChain(), dl, DataOp, N->getBasePtr(), in PromoteIntOp_MSTORE()
3219 SDValue Ptr = N->getBasePtr(); in ExpandIntRes_LOAD()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelDAGToDAG.cpp161 LD->getBasePtr(), LD->getChain()); in selectIndexedLoad()
324 SDValue BasePtr = ST->getBasePtr(); in select()
370 SDValue Ptr = LD->getBasePtr(); in select()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp1198 if (!selectBDVAddr12Only(Load->getBasePtr(), ElemV, Base, Disp, Index) || in tryGather()
1232 if (!selectBDVAddr12Only(Store->getBasePtr(), ElemV, Base, Disp, Index) || in tryScatter()
1276 if (LoadNode->getBasePtr() != StoreNode->getBasePtr() || in isFusableLoadOpStorePattern()
1393 if (!selectBDAddr20Only(StoreNode->getBasePtr(), Base, Disp)) in tryFoldLoadStoreIntoMemOperand()
1448 if (SystemZISD::isPCREL(Load->getBasePtr().getOpcode())) in storeLoadCanUseMVC()
1451 if (SystemZISD::isPCREL(Store->getBasePtr().getOpcode())) in storeLoadCanUseMVC()
1471 SDValue BasePtr = MemAccess->getBasePtr(); in storeLoadIsAligned()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelDAGToDAG.cpp346 LD->getBasePtr(), LD->getChain())); in tryIndexedLoad()
362 SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() }; in tryIndexedBinOp()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp423 SDValue BasePtr = LD->getBasePtr(); in LowerLOAD()
496 SDValue BasePtr = ST->getBasePtr(); in LowerSTORE()
947 N->getChain(), N->getBasePtr(), N->getPointerInfo(), in LowerATOMIC_LOAD()
955 N->getBasePtr(), N->getPointerInfo(), MVT::i16, in LowerATOMIC_LOAD()
961 N->getBasePtr(), N->getPointerInfo(), MVT::i8, in LowerATOMIC_LOAD()
977 return DAG.getStore(N->getChain(), SDLoc(Op), N->getVal(), N->getBasePtr(), in LowerATOMIC_STORE()
985 N->getBasePtr(), N->getPointerInfo(), MVT::i16, in LowerATOMIC_STORE()
991 N->getBasePtr(), N->getPointerInfo(), MVT::i8, in LowerATOMIC_STORE()
1802 return DAG.getMemmove(Chain, dl, ST->getBasePtr(), LD->getBasePtr(), in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAGNodes.h1353 const SDValue &getBasePtr() const {
1413 const SDValue &getBasePtr() const { return getOperand(1); }
2282 const SDValue &getBasePtr() const { return getOperand(1); }
2313 const SDValue &getBasePtr() const { return getOperand(2); }
2380 const SDValue &getBasePtr() const { return getOperand(1); }
2417 const SDValue &getBasePtr() const { return getOperand(2); }
2461 const SDValue &getBasePtr() const { return getOperand(3); }
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp1275 DAG.getLoad(MVT::f64, DL, LdNode->getChain(), LdNode->getBasePtr(), in lowerLoadF128()
1279 EVT AddrVT = LdNode->getBasePtr().getValueType(); in lowerLoadF128()
1280 SDValue HiPtr = DAG.getNode(ISD::ADD, DL, AddrVT, LdNode->getBasePtr(), in lowerLoadF128()
1308 SDValue BasePtr = LdNode->getBasePtr(); in lowerLOAD()
1344 StNode->getBasePtr(), MachinePointerInfo(), Alignment, in lowerStoreF128()
1347 EVT AddrVT = StNode->getBasePtr().getValueType(); in lowerStoreF128()
1348 SDValue HiPtr = DAG.getNode(ISD::ADD, DL, AddrVT, StNode->getBasePtr(), in lowerStoreF128()
1362 SDValue BasePtr = StNode->getBasePtr(); in lowerSTORE()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DEarlyCSE.cpp308 GCR->getBasePtr(), GCR->getDerivedPtr()); in getHashValueImpl()
375 GCR1->getBasePtr() == GCR2->getBasePtr() && in isEqualImpl()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1072 SDValue BasePtr = Store->getBasePtr(); in lowerPrivateTruncStore()
1144 SDValue Ptr = StoreNode->getBasePtr(); in LowerSTORE()
1303 SDValue BasePtr = Load->getBasePtr(); in lowerPrivateExtLoad()
1365 SDValue Ptr = LoadNode->getBasePtr(); in LowerLOAD()
1708 SDValue Ptr = LoadNode->getBasePtr(); in constBufferLoad()
1967 SDValue Ptr = LoadNode->getBasePtr(); in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp68 SDValue Base = LD->getBasePtr(); in SelectIndexedLoad()
465 SDValue Base = ST->getBasePtr(); in SelectIndexedStore()
973 SDValue LDBasePtr = cast<MemSDNode>(SYNode)->getBasePtr(); in isMemOPCandidate()
974 SDValue STBasePtr = cast<MemSDNode>(UUse)->getBasePtr(); in isMemOPCandidate()
2255 SDValue BasePtr = cast<MemSDNode>(N)->getBasePtr(); in rebalanceAddressTrees()
H A DHexagonISelLowering.cpp2932 LN->getChain(), LN->getBasePtr(), LN->getOffset(), LN->getPointerInfo(), in LowerLoad()
2939 if (!validateConstPtrAlignment(LN->getBasePtr(), ClaimAlign, dl, DAG)) in LowerLoad()
2963 SDValue NS = DAG.getStore(SN->getChain(), dl, TC, SN->getBasePtr(), in LowerStore()
2966 NS = DAG.getIndexedStore(NS, dl, SN->getBasePtr(), SN->getOffset(), in LowerStore()
2973 if (!validateConstPtrAlignment(SN->getBasePtr(), ClaimAlign, dl, DAG)) in LowerStore()
3030 SDValue Base = LN->getBasePtr(); in LowerUnalignedLoad()
3582 std::pair<SDValue,int> BO = getBaseAndOffset(L->getBasePtr()); in shouldReduceLoadWidth()
H A DHexagonISelLoweringHVX.cpp1707 SDValue Base = MaskN->getBasePtr(); in LowerHvxMaskedOp()
1814 SDValue Base0 = MemN->getBasePtr(); in SplitHvxMemOp()
1890 SDValue Base = LoadN->getBasePtr(); in WidenHvxLoad()
1922 SDValue Base = StoreN->getBasePtr(); in WidenHvxStore()
/freebsd-13.1/contrib/llvm-project/llvm/lib/IR/
H A DIntrinsicInst.cpp566 Value *GCRelocateInst::getBasePtr() const { in getBasePtr() function in GCRelocateInst
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp2745 DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LdNode->getBasePtr(), in LowerF128Load()
2747 EVT addrVT = LdNode->getBasePtr().getValueType(); in LowerF128Load()
2749 LdNode->getBasePtr(), in LowerF128Load()
2813 StNode->getBasePtr(), StNode->getPointerInfo(), in LowerF128Store()
2815 EVT addrVT = StNode->getBasePtr().getValueType(); in LowerF128Store()
2817 StNode->getBasePtr(), in LowerF128Store()
2839 St->getChain(), dl, Val, St->getBasePtr(), St->getPointerInfo(), in LowerSTORE()
3408 Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32, in ReplaceNodeResults()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp4592 SDValue Ptr = Ld->getBasePtr(); in MatchingStackOffset()
8390 SDValue Ptr = LD->getBasePtr(); in LowerAsSplatVectorLoad()
24331 SDValue Ptr0 = Store->getBasePtr(); in splitVectorStore()
30170 SDValue BasePtr = N->getBasePtr(); in LowerMSCATTER()
44655 SDValue Base = Ld->getBasePtr(); in getIndexFromUnindexedLoad()
45778 SDValue Ptr1 = Ld->getBasePtr(); in combineLoad()
45818 SDValue Ptr = Ld->getBasePtr(); in combineLoad()
45904 Addr = MaskedOp->getBasePtr(); in getParamsForOneTrueMaskedElt()
48933 SDValue Base = GorS->getBasePtr(); in combineGatherScatter()
51430 return Ld->getBasePtr() == St->getBasePtr(); in IsDesirableToPromoteOp()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp2941 Ptr = LD->getBasePtr(); in getPreIndexedAddressParts()
2945 Ptr = ST->getBasePtr(); in getPreIndexedAddressParts()
7706 SDValue BasePtr = LD->getBasePtr(); in LowerLOAD()
7731 SDValue BasePtr = ST->getBasePtr(); in LowerSTORE()
8234 RLI.Ptr = LD->getBasePtr(); in canReuseLoadAddress()
9157 LD->getBasePtr(), // Ptr in LowerBUILD_VECTOR()
10588 SDValue BasePtr = LN->getBasePtr(); in LowerVectorLoad()
12831 SDValue Loc = LS->getBasePtr(); in isConsecutiveLS()
14217 Base = LD->getBasePtr(); in expandVSXLoadForLE()
14286 Base = ST->getBasePtr(); in expandVSXStoreForLE()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp2877 SDValue Ptr = Ld->getBasePtr(); in MatchingStackOffset()
5517 SDValue Ptr = Ld->getBasePtr(); in expandf64Toi32()
15584 SDValue BasePtr = St->getBasePtr(); in PerformTruncatingStoreCombine()
18665 Ptr = LD->getBasePtr(); in getPreIndexedAddressParts()
18670 Ptr = ST->getBasePtr(); in getPreIndexedAddressParts()
18674 Ptr = LD->getBasePtr(); in getPreIndexedAddressParts()
18680 Ptr = ST->getBasePtr(); in getPreIndexedAddressParts()
18724 Ptr = LD->getBasePtr(); in getPostIndexedAddressParts()
18730 Ptr = ST->getBasePtr(); in getPostIndexedAddressParts()
18735 Ptr = LD->getBasePtr(); in getPostIndexedAddressParts()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp4332 SDValue BasePtr = MGT->getBasePtr(); in LowerMGATHER()
4438 SDValue BasePtr = MSC->getBasePtr(); in LowerMSCATTER()
4637 SDValue Base = StoreNode->getBasePtr(); in LowerSTORE()
4661 SDValue Base = LoadNode->getBasePtr(); in LowerLOAD()
11315 const SDValue &Base = Mem->getBasePtr(); in shouldReduceLoadWidth()
14596 SDValue BasePtr = St.getBasePtr(); in splitStoreSplat()
14981 SDValue BasePtr = S->getBasePtr(); in splitStores()
17019 Ptr = LD->getBasePtr(); in getPreIndexedAddressParts()
17022 Ptr = ST->getBasePtr(); in getPreIndexedAddressParts()
17040 Ptr = LD->getBasePtr(); in getPostIndexedAddressParts()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp1859 SDValue NewAddr = DAG.getMemBasePlusOffset(Ld->getBasePtr(), in lowerVECTOR_SHUFFLE()
2052 SDValue L = DAG.getLoad(NewVT, DL, Load->getChain(), Load->getBasePtr(), in expandUnalignedRVVLoad()
2084 return DAG.getStore(Store->getChain(), DL, StoredVal, Store->getBasePtr(), in expandUnalignedRVVStore()
4337 {Store->getChain(), NewValue, Store->getBasePtr(), VL}, in lowerFixedLengthVectorStoreToRVV()
4366 Load->getBasePtr(), Mask, VL}; in lowerMLOAD()
4402 {Store->getChain(), IntID, Val, Store->getBasePtr(), Mask, VL}, in lowerMSTORE()
4618 assert(MGN->getBasePtr().getSimpleValueType() == XLenVT && in lowerMGATHER()
4662 Ops.push_back(MGN->getBasePtr()); in lowerMGATHER()
4699 assert(MSN->getBasePtr().getSimpleValueType() == XLenVT && in lowerMSCATTER()
4742 Ops.push_back(MSN->getBasePtr()); in lowerMSCATTER()
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