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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrFormatsC.td51 class RVInst16CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
58 let Inst{15-13} = funct3;
67 class RVInst16CSS<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
74 let Inst{15-13} = funct3;
85 let Inst{15-13} = funct3;
93 class RVInst16CL<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
99 let Inst{15-13} = funct3;
108 class RVInst16CS<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
114 let Inst{15-13} = funct3;
139 let Inst{15-13} = funct3;
[all …]
H A DRISCVInstrFormats.td234 let Inst{14-12} = funct3;
251 let Inst{14-12} = funct3;
262 bits<3> funct3;
269 let Inst{14-12} = funct3;
287 let Inst{14-12} = funct3;
297 bits<3> funct3;
303 let Inst{14-12} = funct3;
317 let Inst{14-12} = funct3;
333 let Inst{14-12} = funct3;
348 let Inst{14-12} = funct3;
[all …]
H A DRISCVInstrInfoA.td37 class LR_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
38 : RVInstRAtomic<0b00010, aq, rl, funct3, OPC_AMO,
44 multiclass LR_r_aq_rl<bits<3> funct3, string opcodestr> {
45 def "" : LR_r<0, 0, funct3, opcodestr>;
46 def _AQ : LR_r<1, 0, funct3, opcodestr # ".aq">;
47 def _RL : LR_r<0, 1, funct3, opcodestr # ".rl">;
48 def _AQ_RL : LR_r<1, 1, funct3, opcodestr # ".aqrl">;
53 : RVInstRAtomic<funct5, aq, rl, funct3, OPC_AMO,
58 def "" : AMO_rr<funct5, 0, 0, funct3, opcodestr>;
59 def _AQ : AMO_rr<funct5, 1, 0, funct3, opcodestr # ".aq">;
[all …]
H A DRISCVInstrInfoF.td59 (ins FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, frmarg:$funct3),
60 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
67 class FPALUS_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
68 : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR32:$rd),
74 (ins FPR32:$rs1, FPR32:$rs2, frmarg:$funct3), opcodestr,
75 "$rd, $rs1, $rs2, $funct3">;
82 class FPUnaryOp_r<bits<7> funct7, bits<3> funct3, RegisterClass rdty,
91 (ins rs1ty:$rs1, frmarg:$funct3), opcodestr,
92 "$rd, $rs1, $funct3">;
100 class FPCmpS_rr<bits<3> funct3, string opcodestr>
[all …]
H A DRISCVInstrInfoD.td35 (ins FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, frmarg:$funct3),
36 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
43 class FPALUD_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
44 : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR64:$rd),
50 (ins FPR64:$rs1, FPR64:$rs2, frmarg:$funct3), opcodestr,
51 "$rd, $rs1, $rs2, $funct3">;
58 class FPCmpD_rr<bits<3> funct3, string opcodestr>
59 : RVInstR<0b1010001, funct3, OPC_OP_FP, (outs GPR:$rd),
H A DRISCVInstrInfoZfh.td37 (ins FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, frmarg:$funct3),
38 opcodestr, "$rd, $rs1, $rs2, $rs3, $funct3">;
45 class FPALUH_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
46 : RVInstR<funct7, funct3, OPC_OP_FP, (outs FPR16:$rd),
52 (ins FPR16:$rs1, FPR16:$rs2, frmarg:$funct3), opcodestr,
53 "$rd, $rs1, $rs2, $funct3">;
60 class FPCmpH_rr<bits<3> funct3, string opcodestr>
61 : RVInstR<0b1010010, funct3, OPC_OP_FP, (outs GPR:$rd),
H A DRISCVInstrInfo.td380 class BranchCC_rri<bits<3> funct3, string opcodestr>
381 : RVInstB<funct3, OPC_BRANCH, (outs),
390 class Load_ri<bits<3> funct3, string opcodestr>
398 class Store_rri<bits<3> funct3, string opcodestr>
399 : RVInstS<funct3, OPC_STORE, (outs),
404 class ALU_ri<bits<3> funct3, string opcodestr>
417 class ALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr>
423 class CSR_ir<bits<3> funct3, string opcodestr>
429 class CSR_ii<bits<3> funct3, string opcodestr>
430 : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd),
[all …]
H A DRISCVInstrInfoC.td222 class CStackLoad<bits<3> funct3, string OpcodeStr,
224 : RVInst16CI<funct3, 0b10, (outs cls:$rd), (ins SP:$rs1, opnd:$imm),
228 class CStackStore<bits<3> funct3, string OpcodeStr,
230 : RVInst16CSS<funct3, 0b10, (outs), (ins cls:$rs2, SP:$rs1, opnd:$imm),
234 class CLoad_ri<bits<3> funct3, string OpcodeStr,
236 : RVInst16CL<funct3, 0b00, (outs cls:$rd), (ins GPRC:$rs1, opnd:$imm),
240 class CStore_rri<bits<3> funct3, string OpcodeStr,
242 : RVInst16CS<funct3, 0b00, (outs), (ins cls:$rs2, GPRC:$rs1, opnd:$imm),
246 class Bcz<bits<3> funct3, string OpcodeStr,
248 : RVInst16CB<funct3, 0b01, (outs), (ins cls:$rs1, simm9_lsb0:$imm),
H A DRISCVInstrInfoB.td197 class RVBUnary<bits<7> funct7, bits<5> funct5, bits<3> funct3,
199 : RVInstR<funct7, funct3, opcode, (outs GPR:$rd), (ins GPR:$rs1),
207 : RVInstIShift<imm11_7, funct3, opcode, (outs GPR:$rd),
214 : RVInstIShiftW<imm11_5, funct3, opcode, (outs GPR:$rd),
220 class RVBShfl_ri<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
222 : RVInstIShiftW<imm11_5, funct3, opcode, (outs GPR:$rd),
227 class RVBTernaryR<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode,
229 : RVInstR4<funct2, funct3, opcode, (outs GPR:$rd),
234 class RVBTernaryImm6<bits<3> funct3, RISCVOpcode opcode,
247 let Inst{14-12} = funct3;
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/freebsd-13.1/contrib/llvm-project/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_linux.cpp1972 unsigned funct3 = (faulty_instruction >> 12) & 0x7; // bits 12-14, inclusive in GetWriteFlag() local
1975 switch (funct3) { in GetWriteFlag()
1989 switch (funct3) { in GetWriteFlag()
2002 switch (funct3) { in GetWriteFlag()
2012 switch (funct3) { in GetWriteFlag()