1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2000 Cameron Grant <[email protected]>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHERIN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THEPOSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 #ifdef HAVE_KERNEL_OPTION_HEADERS
30 #include "opt_snd.h"
31 #endif
32
33 #include <dev/sound/pcm/sound.h>
34 #include <dev/sound/pcm/ac97.h>
35
36 #include <dev/pci/pcireg.h>
37 #include <dev/pci/pcivar.h>
38
39 #include <dev/sound/pci/ds1.h>
40 #include <dev/sound/pci/ds1-fw.h>
41
42 SND_DECLARE_FILE("$FreeBSD$");
43
44 /* -------------------------------------------------------------------- */
45
46 #define DS1_CHANS 4
47 #define DS1_RECPRIMARY 0
48 #define DS1_IRQHZ ((48000 << 8) / 256)
49 #define DS1_BUFFSIZE 4096
50
51 struct pbank {
52 volatile u_int32_t Format;
53 volatile u_int32_t LoopDefault;
54 volatile u_int32_t PgBase;
55 volatile u_int32_t PgLoop;
56 volatile u_int32_t PgLoopEnd;
57 volatile u_int32_t PgLoopFrac;
58 volatile u_int32_t PgDeltaEnd;
59 volatile u_int32_t LpfKEnd;
60 volatile u_int32_t EgGainEnd;
61 volatile u_int32_t LchGainEnd;
62 volatile u_int32_t RchGainEnd;
63 volatile u_int32_t Effect1GainEnd;
64 volatile u_int32_t Effect2GainEnd;
65 volatile u_int32_t Effect3GainEnd;
66 volatile u_int32_t LpfQ;
67 volatile u_int32_t Status;
68 volatile u_int32_t NumOfFrames;
69 volatile u_int32_t LoopCount;
70 volatile u_int32_t PgStart;
71 volatile u_int32_t PgStartFrac;
72 volatile u_int32_t PgDelta;
73 volatile u_int32_t LpfK;
74 volatile u_int32_t EgGain;
75 volatile u_int32_t LchGain;
76 volatile u_int32_t RchGain;
77 volatile u_int32_t Effect1Gain;
78 volatile u_int32_t Effect2Gain;
79 volatile u_int32_t Effect3Gain;
80 volatile u_int32_t LpfD1;
81 volatile u_int32_t LpfD2;
82 };
83
84 struct rbank {
85 volatile u_int32_t PgBase;
86 volatile u_int32_t PgLoopEnd;
87 volatile u_int32_t PgStart;
88 volatile u_int32_t NumOfLoops;
89 };
90
91 struct sc_info;
92
93 /* channel registers */
94 struct sc_pchinfo {
95 int run, spd, dir, fmt;
96 struct snd_dbuf *buffer;
97 struct pcm_channel *channel;
98 volatile struct pbank *lslot, *rslot;
99 int lsnum, rsnum;
100 struct sc_info *parent;
101 };
102
103 struct sc_rchinfo {
104 int run, spd, dir, fmt, num;
105 struct snd_dbuf *buffer;
106 struct pcm_channel *channel;
107 volatile struct rbank *slot;
108 struct sc_info *parent;
109 };
110
111 /* device private data */
112 struct sc_info {
113 device_t dev;
114 u_int32_t type, rev;
115 u_int32_t cd2id, ctrlbase;
116
117 bus_space_tag_t st;
118 bus_space_handle_t sh;
119 bus_dma_tag_t buffer_dmat, control_dmat;
120 bus_dmamap_t map;
121
122 struct resource *reg, *irq;
123 int regid, irqid;
124 void *ih;
125 struct mtx *lock;
126
127 void *regbase;
128 u_int32_t *pbase, pbankbase, pbanksize;
129 volatile struct pbank *pbank[2 * 64];
130 volatile struct rbank *rbank;
131 int pslotfree, currbank, pchn, rchn;
132 unsigned int bufsz;
133
134 struct sc_pchinfo pch[DS1_CHANS];
135 struct sc_rchinfo rch[2];
136 };
137
138 struct {
139 u_int32_t dev, subdev;
140 char *name;
141 u_int32_t *mcode;
142 } ds_devs[] = {
143 {0x00041073, 0, "Yamaha DS-1 (YMF724)", CntrlInst},
144 {0x000d1073, 0, "Yamaha DS-1E (YMF724F)", CntrlInst1E},
145 {0x00051073, 0, "Yamaha DS-1? (YMF734)", CntrlInst},
146 {0x00081073, 0, "Yamaha DS-1? (YMF737)", CntrlInst},
147 {0x00201073, 0, "Yamaha DS-1? (YMF738)", CntrlInst},
148 {0x00061073, 0, "Yamaha DS-1? (YMF738_TEG)", CntrlInst},
149 {0x000a1073, 0x00041073, "Yamaha DS-1 (YMF740)", CntrlInst},
150 {0x000a1073, 0x000a1073, "Yamaha DS-1 (YMF740B)", CntrlInst},
151 {0x000a1073, 0x53328086, "Yamaha DS-1 (YMF740I)", CntrlInst},
152 {0x000a1073, 0, "Yamaha DS-1 (YMF740?)", CntrlInst},
153 {0x000c1073, 0, "Yamaha DS-1E (YMF740C)", CntrlInst1E},
154 {0x00101073, 0, "Yamaha DS-1E (YMF744)", CntrlInst1E},
155 {0x00121073, 0, "Yamaha DS-1E (YMF754)", CntrlInst1E},
156 {0, 0, NULL, NULL}
157 };
158
159 /* -------------------------------------------------------------------- */
160
161 /*
162 * prototypes
163 */
164
165 /* stuff */
166 static int ds_init(struct sc_info *);
167 static void ds_intr(void *);
168
169 /* talk to the card */
170 static u_int32_t ds_rd(struct sc_info *, int, int);
171 static void ds_wr(struct sc_info *, int, u_int32_t, int);
172
173 /* -------------------------------------------------------------------- */
174
175 static u_int32_t ds_recfmt[] = {
176 SND_FORMAT(AFMT_U8, 1, 0),
177 SND_FORMAT(AFMT_U8, 2, 0),
178 SND_FORMAT(AFMT_S8, 1, 0),
179 SND_FORMAT(AFMT_S8, 2, 0),
180 SND_FORMAT(AFMT_S16_LE, 1, 0),
181 SND_FORMAT(AFMT_S16_LE, 2, 0),
182 SND_FORMAT(AFMT_U16_LE, 1, 0),
183 SND_FORMAT(AFMT_U16_LE, 2, 0),
184 0
185 };
186 static struct pcmchan_caps ds_reccaps = {4000, 48000, ds_recfmt, 0};
187
188 static u_int32_t ds_playfmt[] = {
189 SND_FORMAT(AFMT_U8, 1, 0),
190 SND_FORMAT(AFMT_U8, 2, 0),
191 /* SND_FORMAT(AFMT_S16_LE, 1, 0), */
192 SND_FORMAT(AFMT_S16_LE, 2, 0),
193 0
194 };
195 static struct pcmchan_caps ds_playcaps = {4000, 96000, ds_playfmt, 0};
196
197 /* -------------------------------------------------------------------- */
198 /* Hardware */
199 static u_int32_t
ds_rd(struct sc_info * sc,int regno,int size)200 ds_rd(struct sc_info *sc, int regno, int size)
201 {
202 switch (size) {
203 case 1:
204 return bus_space_read_1(sc->st, sc->sh, regno);
205 case 2:
206 return bus_space_read_2(sc->st, sc->sh, regno);
207 case 4:
208 return bus_space_read_4(sc->st, sc->sh, regno);
209 default:
210 return 0xffffffff;
211 }
212 }
213
214 static void
ds_wr(struct sc_info * sc,int regno,u_int32_t data,int size)215 ds_wr(struct sc_info *sc, int regno, u_int32_t data, int size)
216 {
217 switch (size) {
218 case 1:
219 bus_space_write_1(sc->st, sc->sh, regno, data);
220 break;
221 case 2:
222 bus_space_write_2(sc->st, sc->sh, regno, data);
223 break;
224 case 4:
225 bus_space_write_4(sc->st, sc->sh, regno, data);
226 break;
227 }
228 }
229
230 static void
wrl(struct sc_info * sc,u_int32_t * ptr,u_int32_t val)231 wrl(struct sc_info *sc, u_int32_t *ptr, u_int32_t val)
232 {
233 *(volatile u_int32_t *)ptr = val;
234 bus_space_barrier(sc->st, sc->sh, 0, 0, BUS_SPACE_BARRIER_WRITE);
235 }
236
237 /* -------------------------------------------------------------------- */
238 /* ac97 codec */
239 static int
ds_cdbusy(struct sc_info * sc,int sec)240 ds_cdbusy(struct sc_info *sc, int sec)
241 {
242 int i, reg;
243
244 reg = sec? YDSXGR_SECSTATUSADR : YDSXGR_PRISTATUSADR;
245 i = YDSXG_AC97TIMEOUT;
246 while (i > 0) {
247 if (!(ds_rd(sc, reg, 2) & 0x8000))
248 return 0;
249 i--;
250 }
251 return ETIMEDOUT;
252 }
253
254 static u_int32_t
ds_initcd(kobj_t obj,void * devinfo)255 ds_initcd(kobj_t obj, void *devinfo)
256 {
257 struct sc_info *sc = (struct sc_info *)devinfo;
258 u_int32_t x;
259
260 x = pci_read_config(sc->dev, PCIR_DSXGCTRL, 1);
261 if (x & 0x03) {
262 pci_write_config(sc->dev, PCIR_DSXGCTRL, x & ~0x03, 1);
263 pci_write_config(sc->dev, PCIR_DSXGCTRL, x | 0x03, 1);
264 pci_write_config(sc->dev, PCIR_DSXGCTRL, x & ~0x03, 1);
265 /*
266 * The YMF740 on some Intel motherboards requires a pretty
267 * hefty delay after this reset for some reason... Otherwise:
268 * "pcm0: ac97 codec init failed"
269 * Maybe this is needed for all YMF740's?
270 * 400ms and 500ms here seem to work, 300ms does not.
271 *
272 * do it for all chips -cg
273 */
274 DELAY(500000);
275 }
276
277 return ds_cdbusy(sc, 0)? 0 : 1;
278 }
279
280 static int
ds_rdcd(kobj_t obj,void * devinfo,int regno)281 ds_rdcd(kobj_t obj, void *devinfo, int regno)
282 {
283 struct sc_info *sc = (struct sc_info *)devinfo;
284 int sec, cid, i;
285 u_int32_t cmd, reg;
286
287 sec = regno & 0x100;
288 regno &= 0xff;
289 cid = sec? (sc->cd2id << 8) : 0;
290 reg = sec? YDSXGR_SECSTATUSDATA : YDSXGR_PRISTATUSDATA;
291 if (sec && cid == 0)
292 return 0xffffffff;
293
294 cmd = YDSXG_AC97READCMD | cid | regno;
295 ds_wr(sc, YDSXGR_AC97CMDADR, cmd, 2);
296
297 if (ds_cdbusy(sc, sec))
298 return 0xffffffff;
299
300 if (sc->type == 11 && sc->rev < 2)
301 for (i = 0; i < 600; i++)
302 ds_rd(sc, reg, 2);
303
304 return ds_rd(sc, reg, 2);
305 }
306
307 static int
ds_wrcd(kobj_t obj,void * devinfo,int regno,u_int32_t data)308 ds_wrcd(kobj_t obj, void *devinfo, int regno, u_int32_t data)
309 {
310 struct sc_info *sc = (struct sc_info *)devinfo;
311 int sec, cid;
312 u_int32_t cmd;
313
314 sec = regno & 0x100;
315 regno &= 0xff;
316 cid = sec? (sc->cd2id << 8) : 0;
317 if (sec && cid == 0)
318 return ENXIO;
319
320 cmd = YDSXG_AC97WRITECMD | cid | regno;
321 cmd <<= 16;
322 cmd |= data;
323 ds_wr(sc, YDSXGR_AC97CMDDATA, cmd, 4);
324
325 return ds_cdbusy(sc, sec);
326 }
327
328 static kobj_method_t ds_ac97_methods[] = {
329 KOBJMETHOD(ac97_init, ds_initcd),
330 KOBJMETHOD(ac97_read, ds_rdcd),
331 KOBJMETHOD(ac97_write, ds_wrcd),
332 KOBJMETHOD_END
333 };
334 AC97_DECLARE(ds_ac97);
335
336 /* -------------------------------------------------------------------- */
337
338 static void
ds_enadsp(struct sc_info * sc,int on)339 ds_enadsp(struct sc_info *sc, int on)
340 {
341 u_int32_t v, i;
342
343 v = on? 1 : 0;
344 if (on) {
345 ds_wr(sc, YDSXGR_CONFIG, 0x00000001, 4);
346 } else {
347 if (ds_rd(sc, YDSXGR_CONFIG, 4))
348 ds_wr(sc, YDSXGR_CONFIG, 0x00000000, 4);
349 i = YDSXG_WORKBITTIMEOUT;
350 while (i > 0) {
351 if (!(ds_rd(sc, YDSXGR_CONFIG, 4) & 0x00000002))
352 break;
353 i--;
354 }
355 }
356 }
357
358 static volatile struct pbank *
ds_allocpslot(struct sc_info * sc)359 ds_allocpslot(struct sc_info *sc)
360 {
361 int slot;
362
363 if (sc->pslotfree > 63)
364 return NULL;
365 slot = sc->pslotfree++;
366 return sc->pbank[slot * 2];
367 }
368
369 static int
ds_initpbank(volatile struct pbank * pb,int ch,int stereo,int b16,u_int32_t rate,bus_addr_t base,u_int32_t len)370 ds_initpbank(volatile struct pbank *pb, int ch, int stereo, int b16, u_int32_t rate, bus_addr_t base, u_int32_t len)
371 {
372 u_int32_t lv[] = {1, 1, 0, 0, 0};
373 u_int32_t rv[] = {1, 0, 1, 0, 0};
374 u_int32_t e1[] = {0, 0, 0, 0, 0};
375 u_int32_t e2[] = {1, 0, 0, 1, 0};
376 u_int32_t e3[] = {1, 0, 0, 0, 1};
377 int ss, i;
378 u_int32_t delta;
379
380 struct {
381 int rate, fK, fQ;
382 } speedinfo[] = {
383 { 100, 0x00570000, 0x35280000},
384 { 2000, 0x06aa0000, 0x34a70000},
385 { 8000, 0x18b20000, 0x32020000},
386 {11025, 0x20930000, 0x31770000},
387 {16000, 0x2b9a0000, 0x31390000},
388 {22050, 0x35a10000, 0x31c90000},
389 {32000, 0x3eaa0000, 0x33d00000},
390 /* {44100, 0x04646000, 0x370a0000},
391 */ {48000, 0x40000000, 0x40000000},
392 };
393
394 ss = b16? 1 : 0;
395 ss += stereo? 1 : 0;
396 delta = (65536 * rate) / 48000;
397 i = 0;
398 while (i < 7 && speedinfo[i].rate < rate)
399 i++;
400
401 pb->Format = stereo? 0x00010000 : 0;
402 pb->Format |= b16? 0 : 0x80000000;
403 pb->Format |= (stereo && (ch == 2 || ch == 4))? 0x00000001 : 0;
404 pb->LoopDefault = 0;
405 pb->PgBase = base;
406 pb->PgLoop = 0;
407 pb->PgLoopEnd = len >> ss;
408 pb->PgLoopFrac = 0;
409 pb->Status = 0;
410 pb->NumOfFrames = 0;
411 pb->LoopCount = 0;
412 pb->PgStart = 0;
413 pb->PgStartFrac = 0;
414 pb->PgDelta = pb->PgDeltaEnd = delta << 12;
415 pb->LpfQ = speedinfo[i].fQ;
416 pb->LpfK = pb->LpfKEnd = speedinfo[i].fK;
417 pb->LpfD1 = pb->LpfD2 = 0;
418 pb->EgGain = pb->EgGainEnd = 0x40000000;
419 pb->LchGain = pb->LchGainEnd = lv[ch] * 0x40000000;
420 pb->RchGain = pb->RchGainEnd = rv[ch] * 0x40000000;
421 pb->Effect1Gain = pb->Effect1GainEnd = e1[ch] * 0x40000000;
422 pb->Effect2Gain = pb->Effect2GainEnd = e2[ch] * 0x40000000;
423 pb->Effect3Gain = pb->Effect3GainEnd = e3[ch] * 0x40000000;
424
425 return 0;
426 }
427
428 static void
ds_enapslot(struct sc_info * sc,int slot,int go)429 ds_enapslot(struct sc_info *sc, int slot, int go)
430 {
431 wrl(sc, &sc->pbase[slot + 1], go? (sc->pbankbase + 2 * slot * sc->pbanksize) : 0);
432 /* printf("pbase[%d] = 0x%x\n", slot + 1, go? (sc->pbankbase + 2 * slot * sc->pbanksize) : 0); */
433 }
434
435 static void
ds_setuppch(struct sc_pchinfo * ch)436 ds_setuppch(struct sc_pchinfo *ch)
437 {
438 int stereo, b16, c, sz;
439 bus_addr_t addr;
440
441 stereo = (AFMT_CHANNEL(ch->fmt) > 1)? 1 : 0;
442 b16 = (ch->fmt & AFMT_16BIT)? 1 : 0;
443 c = stereo? 1 : 0;
444 addr = sndbuf_getbufaddr(ch->buffer);
445 sz = sndbuf_getsize(ch->buffer);
446
447 ds_initpbank(ch->lslot, c, stereo, b16, ch->spd, addr, sz);
448 ds_initpbank(ch->lslot + 1, c, stereo, b16, ch->spd, addr, sz);
449 ds_initpbank(ch->rslot, 2, stereo, b16, ch->spd, addr, sz);
450 ds_initpbank(ch->rslot + 1, 2, stereo, b16, ch->spd, addr, sz);
451 }
452
453 static void
ds_setuprch(struct sc_rchinfo * ch)454 ds_setuprch(struct sc_rchinfo *ch)
455 {
456 struct sc_info *sc = ch->parent;
457 int stereo, b16, i, sz, pri;
458 u_int32_t x, y;
459 bus_addr_t addr;
460
461 stereo = (AFMT_CHANNEL(ch->fmt) > 1)? 1 : 0;
462 b16 = (ch->fmt & AFMT_16BIT)? 1 : 0;
463 addr = sndbuf_getbufaddr(ch->buffer);
464 sz = sndbuf_getsize(ch->buffer);
465 pri = (ch->num == DS1_RECPRIMARY)? 1 : 0;
466
467 for (i = 0; i < 2; i++) {
468 ch->slot[i].PgBase = addr;
469 ch->slot[i].PgLoopEnd = sz;
470 ch->slot[i].PgStart = 0;
471 ch->slot[i].NumOfLoops = 0;
472 }
473 x = (b16? 0x00 : 0x01) | (stereo? 0x02 : 0x00);
474 y = (48000 * 4096) / ch->spd;
475 y--;
476 /* printf("pri = %d, x = %d, y = %d\n", pri, x, y); */
477 ds_wr(sc, pri? YDSXGR_ADCFORMAT : YDSXGR_RECFORMAT, x, 4);
478 ds_wr(sc, pri? YDSXGR_ADCSLOTSR : YDSXGR_RECSLOTSR, y, 4);
479 }
480
481 /* -------------------------------------------------------------------- */
482 /* play channel interface */
483 static void *
ds1pchan_init(kobj_t obj,void * devinfo,struct snd_dbuf * b,struct pcm_channel * c,int dir)484 ds1pchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
485 {
486 struct sc_info *sc = devinfo;
487 struct sc_pchinfo *ch;
488
489 KASSERT(dir == PCMDIR_PLAY, ("ds1pchan_init: bad direction"));
490
491 ch = &sc->pch[sc->pchn++];
492 ch->buffer = b;
493 ch->parent = sc;
494 ch->channel = c;
495 ch->dir = dir;
496 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
497 ch->spd = 8000;
498 ch->run = 0;
499 if (sndbuf_alloc(ch->buffer, sc->buffer_dmat, 0, sc->bufsz) != 0)
500 return NULL;
501 else {
502 ch->lsnum = sc->pslotfree;
503 ch->lslot = ds_allocpslot(sc);
504 ch->rsnum = sc->pslotfree;
505 ch->rslot = ds_allocpslot(sc);
506 ds_setuppch(ch);
507 return ch;
508 }
509 }
510
511 static int
ds1pchan_setformat(kobj_t obj,void * data,u_int32_t format)512 ds1pchan_setformat(kobj_t obj, void *data, u_int32_t format)
513 {
514 struct sc_pchinfo *ch = data;
515
516 ch->fmt = format;
517
518 return 0;
519 }
520
521 static u_int32_t
ds1pchan_setspeed(kobj_t obj,void * data,u_int32_t speed)522 ds1pchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
523 {
524 struct sc_pchinfo *ch = data;
525
526 ch->spd = speed;
527
528 return speed;
529 }
530
531 static u_int32_t
ds1pchan_setblocksize(kobj_t obj,void * data,u_int32_t blocksize)532 ds1pchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
533 {
534 struct sc_pchinfo *ch = data;
535 struct sc_info *sc = ch->parent;
536 int drate;
537
538 /* irq rate is fixed at 187.5hz */
539 drate = ch->spd * sndbuf_getalign(ch->buffer);
540 blocksize = roundup2((drate << 8) / DS1_IRQHZ, 4);
541 sndbuf_resize(ch->buffer, sc->bufsz / blocksize, blocksize);
542
543 return blocksize;
544 }
545
546 /* semantic note: must start at beginning of buffer */
547 static int
ds1pchan_trigger(kobj_t obj,void * data,int go)548 ds1pchan_trigger(kobj_t obj, void *data, int go)
549 {
550 struct sc_pchinfo *ch = data;
551 struct sc_info *sc = ch->parent;
552 int stereo;
553
554 if (!PCMTRIG_COMMON(go))
555 return 0;
556 stereo = (AFMT_CHANNEL(ch->fmt) > 1)? 1 : 0;
557 if (go == PCMTRIG_START) {
558 ch->run = 1;
559 ds_setuppch(ch);
560 ds_enapslot(sc, ch->lsnum, 1);
561 ds_enapslot(sc, ch->rsnum, stereo);
562 snd_mtxlock(sc->lock);
563 ds_wr(sc, YDSXGR_MODE, 0x00000003, 4);
564 snd_mtxunlock(sc->lock);
565 } else {
566 ch->run = 0;
567 /* ds_setuppch(ch); */
568 ds_enapslot(sc, ch->lsnum, 0);
569 ds_enapslot(sc, ch->rsnum, 0);
570 }
571
572 return 0;
573 }
574
575 static u_int32_t
ds1pchan_getptr(kobj_t obj,void * data)576 ds1pchan_getptr(kobj_t obj, void *data)
577 {
578 struct sc_pchinfo *ch = data;
579 struct sc_info *sc = ch->parent;
580 volatile struct pbank *bank;
581 int ss;
582 u_int32_t ptr;
583
584 ss = (AFMT_CHANNEL(ch->fmt) > 1)? 1 : 0;
585 ss += (ch->fmt & AFMT_16BIT)? 1 : 0;
586
587 bank = ch->lslot + sc->currbank;
588 /* printf("getptr: %d\n", bank->PgStart << ss); */
589 ptr = bank->PgStart;
590 ptr <<= ss;
591 return ptr;
592 }
593
594 static struct pcmchan_caps *
ds1pchan_getcaps(kobj_t obj,void * data)595 ds1pchan_getcaps(kobj_t obj, void *data)
596 {
597 return &ds_playcaps;
598 }
599
600 static kobj_method_t ds1pchan_methods[] = {
601 KOBJMETHOD(channel_init, ds1pchan_init),
602 KOBJMETHOD(channel_setformat, ds1pchan_setformat),
603 KOBJMETHOD(channel_setspeed, ds1pchan_setspeed),
604 KOBJMETHOD(channel_setblocksize, ds1pchan_setblocksize),
605 KOBJMETHOD(channel_trigger, ds1pchan_trigger),
606 KOBJMETHOD(channel_getptr, ds1pchan_getptr),
607 KOBJMETHOD(channel_getcaps, ds1pchan_getcaps),
608 KOBJMETHOD_END
609 };
610 CHANNEL_DECLARE(ds1pchan);
611
612 /* -------------------------------------------------------------------- */
613 /* record channel interface */
614 static void *
ds1rchan_init(kobj_t obj,void * devinfo,struct snd_dbuf * b,struct pcm_channel * c,int dir)615 ds1rchan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
616 {
617 struct sc_info *sc = devinfo;
618 struct sc_rchinfo *ch;
619
620 KASSERT(dir == PCMDIR_REC, ("ds1rchan_init: bad direction"));
621
622 ch = &sc->rch[sc->rchn];
623 ch->num = sc->rchn++;
624 ch->buffer = b;
625 ch->parent = sc;
626 ch->channel = c;
627 ch->dir = dir;
628 ch->fmt = SND_FORMAT(AFMT_U8, 1, 0);
629 ch->spd = 8000;
630 if (sndbuf_alloc(ch->buffer, sc->buffer_dmat, 0, sc->bufsz) != 0)
631 return NULL;
632 else {
633 ch->slot = (ch->num == DS1_RECPRIMARY)? sc->rbank + 2: sc->rbank;
634 ds_setuprch(ch);
635 return ch;
636 }
637 }
638
639 static int
ds1rchan_setformat(kobj_t obj,void * data,u_int32_t format)640 ds1rchan_setformat(kobj_t obj, void *data, u_int32_t format)
641 {
642 struct sc_rchinfo *ch = data;
643
644 ch->fmt = format;
645
646 return 0;
647 }
648
649 static u_int32_t
ds1rchan_setspeed(kobj_t obj,void * data,u_int32_t speed)650 ds1rchan_setspeed(kobj_t obj, void *data, u_int32_t speed)
651 {
652 struct sc_rchinfo *ch = data;
653
654 ch->spd = speed;
655
656 return speed;
657 }
658
659 static u_int32_t
ds1rchan_setblocksize(kobj_t obj,void * data,u_int32_t blocksize)660 ds1rchan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
661 {
662 struct sc_rchinfo *ch = data;
663 struct sc_info *sc = ch->parent;
664 int drate;
665
666 /* irq rate is fixed at 187.5hz */
667 drate = ch->spd * sndbuf_getalign(ch->buffer);
668 blocksize = roundup2((drate << 8) / DS1_IRQHZ, 4);
669 sndbuf_resize(ch->buffer, sc->bufsz / blocksize, blocksize);
670
671 return blocksize;
672 }
673
674 /* semantic note: must start at beginning of buffer */
675 static int
ds1rchan_trigger(kobj_t obj,void * data,int go)676 ds1rchan_trigger(kobj_t obj, void *data, int go)
677 {
678 struct sc_rchinfo *ch = data;
679 struct sc_info *sc = ch->parent;
680 u_int32_t x;
681
682 if (!PCMTRIG_COMMON(go))
683 return 0;
684 if (go == PCMTRIG_START) {
685 ch->run = 1;
686 ds_setuprch(ch);
687 snd_mtxlock(sc->lock);
688 x = ds_rd(sc, YDSXGR_MAPOFREC, 4);
689 x |= (ch->num == DS1_RECPRIMARY)? 0x02 : 0x01;
690 ds_wr(sc, YDSXGR_MAPOFREC, x, 4);
691 ds_wr(sc, YDSXGR_MODE, 0x00000003, 4);
692 snd_mtxunlock(sc->lock);
693 } else {
694 ch->run = 0;
695 snd_mtxlock(sc->lock);
696 x = ds_rd(sc, YDSXGR_MAPOFREC, 4);
697 x &= ~((ch->num == DS1_RECPRIMARY)? 0x02 : 0x01);
698 ds_wr(sc, YDSXGR_MAPOFREC, x, 4);
699 snd_mtxunlock(sc->lock);
700 }
701
702 return 0;
703 }
704
705 static u_int32_t
ds1rchan_getptr(kobj_t obj,void * data)706 ds1rchan_getptr(kobj_t obj, void *data)
707 {
708 struct sc_rchinfo *ch = data;
709 struct sc_info *sc = ch->parent;
710
711 return ch->slot[sc->currbank].PgStart;
712 }
713
714 static struct pcmchan_caps *
ds1rchan_getcaps(kobj_t obj,void * data)715 ds1rchan_getcaps(kobj_t obj, void *data)
716 {
717 return &ds_reccaps;
718 }
719
720 static kobj_method_t ds1rchan_methods[] = {
721 KOBJMETHOD(channel_init, ds1rchan_init),
722 KOBJMETHOD(channel_setformat, ds1rchan_setformat),
723 KOBJMETHOD(channel_setspeed, ds1rchan_setspeed),
724 KOBJMETHOD(channel_setblocksize, ds1rchan_setblocksize),
725 KOBJMETHOD(channel_trigger, ds1rchan_trigger),
726 KOBJMETHOD(channel_getptr, ds1rchan_getptr),
727 KOBJMETHOD(channel_getcaps, ds1rchan_getcaps),
728 KOBJMETHOD_END
729 };
730 CHANNEL_DECLARE(ds1rchan);
731
732 /* -------------------------------------------------------------------- */
733 /* The interrupt handler */
734 static void
ds_intr(void * p)735 ds_intr(void *p)
736 {
737 struct sc_info *sc = (struct sc_info *)p;
738 u_int32_t i, x;
739
740 snd_mtxlock(sc->lock);
741 i = ds_rd(sc, YDSXGR_STATUS, 4);
742 if (i & 0x00008000)
743 device_printf(sc->dev, "timeout irq\n");
744 if (i & 0x80008000) {
745 ds_wr(sc, YDSXGR_STATUS, i & 0x80008000, 4);
746 sc->currbank = ds_rd(sc, YDSXGR_CTRLSELECT, 4) & 0x00000001;
747
748 x = 0;
749 for (i = 0; i < DS1_CHANS; i++) {
750 if (sc->pch[i].run) {
751 x = 1;
752 snd_mtxunlock(sc->lock);
753 chn_intr(sc->pch[i].channel);
754 snd_mtxlock(sc->lock);
755 }
756 }
757 for (i = 0; i < 2; i++) {
758 if (sc->rch[i].run) {
759 x = 1;
760 snd_mtxunlock(sc->lock);
761 chn_intr(sc->rch[i].channel);
762 snd_mtxlock(sc->lock);
763 }
764 }
765 i = ds_rd(sc, YDSXGR_MODE, 4);
766 if (x)
767 ds_wr(sc, YDSXGR_MODE, i | 0x00000002, 4);
768 }
769 snd_mtxunlock(sc->lock);
770 }
771
772 /* -------------------------------------------------------------------- */
773
774 /*
775 * Probe and attach the card
776 */
777
778 static void
ds_setmap(void * arg,bus_dma_segment_t * segs,int nseg,int error)779 ds_setmap(void *arg, bus_dma_segment_t *segs, int nseg, int error)
780 {
781 struct sc_info *sc = arg;
782
783 sc->ctrlbase = error? 0 : (u_int32_t)segs->ds_addr;
784
785 if (bootverbose) {
786 printf("ds1: setmap (%lx, %lx), nseg=%d, error=%d\n",
787 (unsigned long)segs->ds_addr, (unsigned long)segs->ds_len,
788 nseg, error);
789 }
790 }
791
792 static int
ds_init(struct sc_info * sc)793 ds_init(struct sc_info *sc)
794 {
795 int i;
796 u_int32_t *ci, r, pcs, rcs, ecs, ws, memsz, cb;
797 u_int8_t *t;
798 void *buf;
799
800 ci = ds_devs[sc->type].mcode;
801
802 ds_wr(sc, YDSXGR_NATIVEDACOUTVOL, 0x00000000, 4);
803 ds_enadsp(sc, 0);
804 ds_wr(sc, YDSXGR_MODE, 0x00010000, 4);
805 ds_wr(sc, YDSXGR_MODE, 0x00000000, 4);
806 ds_wr(sc, YDSXGR_MAPOFREC, 0x00000000, 4);
807 ds_wr(sc, YDSXGR_MAPOFEFFECT, 0x00000000, 4);
808 ds_wr(sc, YDSXGR_PLAYCTRLBASE, 0x00000000, 4);
809 ds_wr(sc, YDSXGR_RECCTRLBASE, 0x00000000, 4);
810 ds_wr(sc, YDSXGR_EFFCTRLBASE, 0x00000000, 4);
811 r = ds_rd(sc, YDSXGR_GLOBALCTRL, 2);
812 ds_wr(sc, YDSXGR_GLOBALCTRL, r & ~0x0007, 2);
813
814 for (i = 0; i < YDSXG_DSPLENGTH; i += 4)
815 ds_wr(sc, YDSXGR_DSPINSTRAM + i, DspInst[i >> 2], 4);
816
817 for (i = 0; i < YDSXG_CTRLLENGTH; i += 4)
818 ds_wr(sc, YDSXGR_CTRLINSTRAM + i, ci[i >> 2], 4);
819
820 ds_enadsp(sc, 1);
821
822 pcs = 0;
823 for (i = 100; i > 0; i--) {
824 pcs = ds_rd(sc, YDSXGR_PLAYCTRLSIZE, 4) << 2;
825 if (pcs == sizeof(struct pbank))
826 break;
827 DELAY(1000);
828 }
829 if (pcs != sizeof(struct pbank)) {
830 device_printf(sc->dev, "preposterous playctrlsize (%d)\n", pcs);
831 return -1;
832 }
833 rcs = ds_rd(sc, YDSXGR_RECCTRLSIZE, 4) << 2;
834 ecs = ds_rd(sc, YDSXGR_EFFCTRLSIZE, 4) << 2;
835 ws = ds_rd(sc, YDSXGR_WORKSIZE, 4) << 2;
836
837 memsz = 64 * 2 * pcs + 2 * 2 * rcs + 5 * 2 * ecs + ws;
838 memsz += (64 + 1) * 4;
839
840 if (sc->regbase == NULL) {
841 if (bus_dma_tag_create(bus_get_dma_tag(sc->dev), 2, 0,
842 BUS_SPACE_MAXADDR_32BIT,
843 BUS_SPACE_MAXADDR,
844 NULL, NULL, memsz, 1, memsz, 0, NULL,
845 NULL, &sc->control_dmat))
846 return -1;
847 if (bus_dmamem_alloc(sc->control_dmat, &buf, BUS_DMA_NOWAIT, &sc->map))
848 return -1;
849 if (bus_dmamap_load(sc->control_dmat, sc->map, buf, memsz, ds_setmap, sc, 0) || !sc->ctrlbase) {
850 device_printf(sc->dev, "pcs=%d, rcs=%d, ecs=%d, ws=%d, memsz=%d\n",
851 pcs, rcs, ecs, ws, memsz);
852 return -1;
853 }
854 sc->regbase = buf;
855 } else
856 buf = sc->regbase;
857
858 cb = 0;
859 t = buf;
860 ds_wr(sc, YDSXGR_WORKBASE, sc->ctrlbase + cb, 4);
861 cb += ws;
862 sc->pbase = (u_int32_t *)(t + cb);
863 /* printf("pbase = %p -> 0x%x\n", sc->pbase, sc->ctrlbase + cb); */
864 ds_wr(sc, YDSXGR_PLAYCTRLBASE, sc->ctrlbase + cb, 4);
865 cb += (64 + 1) * 4;
866 sc->rbank = (struct rbank *)(t + cb);
867 ds_wr(sc, YDSXGR_RECCTRLBASE, sc->ctrlbase + cb, 4);
868 cb += 2 * 2 * rcs;
869 ds_wr(sc, YDSXGR_EFFCTRLBASE, sc->ctrlbase + cb, 4);
870 cb += 5 * 2 * ecs;
871
872 sc->pbankbase = sc->ctrlbase + cb;
873 sc->pbanksize = pcs;
874 for (i = 0; i < 64; i++) {
875 wrl(sc, &sc->pbase[i + 1], 0);
876 sc->pbank[i * 2] = (struct pbank *)(t + cb);
877 /* printf("pbank[%d] = %p -> 0x%x; ", i * 2, (struct pbank *)(t + cb), sc->ctrlbase + cb - vtophys(t + cb)); */
878 cb += pcs;
879 sc->pbank[i * 2 + 1] = (struct pbank *)(t + cb);
880 /* printf("pbank[%d] = %p -> 0x%x\n", i * 2 + 1, (struct pbank *)(t + cb), sc->ctrlbase + cb - vtophys(t + cb)); */
881 cb += pcs;
882 }
883 wrl(sc, &sc->pbase[0], DS1_CHANS * 2);
884
885 sc->pchn = sc->rchn = 0;
886 ds_wr(sc, YDSXGR_NATIVEDACOUTVOL, 0x3fff3fff, 4);
887 ds_wr(sc, YDSXGR_NATIVEADCINVOL, 0x3fff3fff, 4);
888 ds_wr(sc, YDSXGR_NATIVEDACINVOL, 0x3fff3fff, 4);
889
890 return 0;
891 }
892
893 static int
ds_uninit(struct sc_info * sc)894 ds_uninit(struct sc_info *sc)
895 {
896 ds_wr(sc, YDSXGR_NATIVEDACOUTVOL, 0x00000000, 4);
897 ds_wr(sc, YDSXGR_NATIVEADCINVOL, 0, 4);
898 ds_wr(sc, YDSXGR_NATIVEDACINVOL, 0, 4);
899 ds_enadsp(sc, 0);
900 ds_wr(sc, YDSXGR_MODE, 0x00010000, 4);
901 ds_wr(sc, YDSXGR_MAPOFREC, 0x00000000, 4);
902 ds_wr(sc, YDSXGR_MAPOFEFFECT, 0x00000000, 4);
903 ds_wr(sc, YDSXGR_PLAYCTRLBASE, 0x00000000, 4);
904 ds_wr(sc, YDSXGR_RECCTRLBASE, 0x00000000, 4);
905 ds_wr(sc, YDSXGR_EFFCTRLBASE, 0x00000000, 4);
906 ds_wr(sc, YDSXGR_GLOBALCTRL, 0, 2);
907
908 bus_dmamap_unload(sc->control_dmat, sc->map);
909 bus_dmamem_free(sc->control_dmat, sc->regbase, sc->map);
910
911 return 0;
912 }
913
914 static int
ds_finddev(u_int32_t dev,u_int32_t subdev)915 ds_finddev(u_int32_t dev, u_int32_t subdev)
916 {
917 int i;
918
919 for (i = 0; ds_devs[i].dev; i++) {
920 if (ds_devs[i].dev == dev &&
921 (ds_devs[i].subdev == subdev || ds_devs[i].subdev == 0))
922 return i;
923 }
924 return -1;
925 }
926
927 static int
ds_pci_probe(device_t dev)928 ds_pci_probe(device_t dev)
929 {
930 int i;
931 u_int32_t subdev;
932
933 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev);
934 i = ds_finddev(pci_get_devid(dev), subdev);
935 if (i >= 0) {
936 device_set_desc(dev, ds_devs[i].name);
937 return BUS_PROBE_DEFAULT;
938 } else
939 return ENXIO;
940 }
941
942 static int
ds_pci_attach(device_t dev)943 ds_pci_attach(device_t dev)
944 {
945 u_int32_t subdev, i;
946 struct sc_info *sc;
947 struct ac97_info *codec = NULL;
948 char status[SND_STATUSLEN];
949
950 sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
951 sc->lock = snd_mtxcreate(device_get_nameunit(dev), "snd_ds1 softc");
952 sc->dev = dev;
953 subdev = (pci_get_subdevice(dev) << 16) | pci_get_subvendor(dev);
954 sc->type = ds_finddev(pci_get_devid(dev), subdev);
955 sc->rev = pci_get_revid(dev);
956
957 pci_enable_busmaster(dev);
958
959 sc->regid = PCIR_BAR(0);
960 sc->reg = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->regid,
961 RF_ACTIVE);
962 if (!sc->reg) {
963 device_printf(dev, "unable to map register space\n");
964 goto bad;
965 }
966
967 sc->st = rman_get_bustag(sc->reg);
968 sc->sh = rman_get_bushandle(sc->reg);
969
970 sc->bufsz = pcm_getbuffersize(dev, 4096, DS1_BUFFSIZE, 65536);
971
972 if (bus_dma_tag_create(/*parent*/bus_get_dma_tag(dev), /*alignment*/2,
973 /*boundary*/0,
974 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
975 /*highaddr*/BUS_SPACE_MAXADDR,
976 /*filter*/NULL, /*filterarg*/NULL,
977 /*maxsize*/sc->bufsz, /*nsegments*/1, /*maxsegz*/0x3ffff,
978 /*flags*/0, /*lockfunc*/NULL,
979 /*lockarg*/NULL, &sc->buffer_dmat) != 0) {
980 device_printf(dev, "unable to create dma tag\n");
981 goto bad;
982 }
983
984 sc->regbase = NULL;
985 if (ds_init(sc) == -1) {
986 device_printf(dev, "unable to initialize the card\n");
987 goto bad;
988 }
989
990 codec = AC97_CREATE(dev, sc, ds_ac97);
991 if (codec == NULL)
992 goto bad;
993 /*
994 * Turn on inverted external amplifier sense flags for few
995 * 'special' boards.
996 */
997 switch (subdev) {
998 case 0x81171033: /* NEC ValueStar (VT550/0) */
999 ac97_setflags(codec, ac97_getflags(codec) | AC97_F_EAPD_INV);
1000 break;
1001 default:
1002 break;
1003 }
1004 mixer_init(dev, ac97_getmixerclass(), codec);
1005
1006 sc->irqid = 0;
1007 sc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irqid,
1008 RF_ACTIVE | RF_SHAREABLE);
1009 if (!sc->irq || snd_setup_intr(dev, sc->irq, INTR_MPSAFE, ds_intr, sc, &sc->ih)) {
1010 device_printf(dev, "unable to map interrupt\n");
1011 goto bad;
1012 }
1013
1014 snprintf(status, SND_STATUSLEN, "at memory 0x%jx irq %jd %s",
1015 rman_get_start(sc->reg), rman_get_start(sc->irq),PCM_KLDSTRING(snd_ds1));
1016
1017 if (pcm_register(dev, sc, DS1_CHANS, 2))
1018 goto bad;
1019 for (i = 0; i < DS1_CHANS; i++)
1020 pcm_addchan(dev, PCMDIR_PLAY, &ds1pchan_class, sc);
1021 for (i = 0; i < 2; i++)
1022 pcm_addchan(dev, PCMDIR_REC, &ds1rchan_class, sc);
1023 pcm_setstatus(dev, status);
1024
1025 return 0;
1026
1027 bad:
1028 if (codec)
1029 ac97_destroy(codec);
1030 if (sc->reg)
1031 bus_release_resource(dev, SYS_RES_MEMORY, sc->regid, sc->reg);
1032 if (sc->ih)
1033 bus_teardown_intr(dev, sc->irq, sc->ih);
1034 if (sc->irq)
1035 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1036 if (sc->buffer_dmat)
1037 bus_dma_tag_destroy(sc->buffer_dmat);
1038 if (sc->control_dmat)
1039 bus_dma_tag_destroy(sc->control_dmat);
1040 if (sc->lock)
1041 snd_mtxfree(sc->lock);
1042 free(sc, M_DEVBUF);
1043 return ENXIO;
1044 }
1045
1046 static int
ds_pci_resume(device_t dev)1047 ds_pci_resume(device_t dev)
1048 {
1049 struct sc_info *sc;
1050
1051 sc = pcm_getdevinfo(dev);
1052
1053 if (ds_init(sc) == -1) {
1054 device_printf(dev, "unable to reinitialize the card\n");
1055 return ENXIO;
1056 }
1057 if (mixer_reinit(dev) == -1) {
1058 device_printf(dev, "unable to reinitialize the mixer\n");
1059 return ENXIO;
1060 }
1061 return 0;
1062 }
1063
1064 static int
ds_pci_detach(device_t dev)1065 ds_pci_detach(device_t dev)
1066 {
1067 int r;
1068 struct sc_info *sc;
1069
1070 r = pcm_unregister(dev);
1071 if (r)
1072 return r;
1073
1074 sc = pcm_getdevinfo(dev);
1075 ds_uninit(sc);
1076 bus_release_resource(dev, SYS_RES_MEMORY, sc->regid, sc->reg);
1077 bus_teardown_intr(dev, sc->irq, sc->ih);
1078 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1079 bus_dma_tag_destroy(sc->buffer_dmat);
1080 bus_dma_tag_destroy(sc->control_dmat);
1081 snd_mtxfree(sc->lock);
1082 free(sc, M_DEVBUF);
1083 return 0;
1084 }
1085
1086 static device_method_t ds1_methods[] = {
1087 /* Device interface */
1088 DEVMETHOD(device_probe, ds_pci_probe),
1089 DEVMETHOD(device_attach, ds_pci_attach),
1090 DEVMETHOD(device_detach, ds_pci_detach),
1091 DEVMETHOD(device_resume, ds_pci_resume),
1092 { 0, 0 }
1093 };
1094
1095 static driver_t ds1_driver = {
1096 "pcm",
1097 ds1_methods,
1098 PCM_SOFTC_SIZE,
1099 };
1100
1101 DRIVER_MODULE(snd_ds1, pci, ds1_driver, pcm_devclass, 0, 0);
1102 MODULE_DEPEND(snd_ds1, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
1103 MODULE_VERSION(snd_ds1, 1);
1104