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/freebsd-13.1/sys/contrib/octeon-sdk/
H A Dcvmx-nand.c551 for (chip=start_chip; chip<stop_chip; chip++) in cvmx_nand_initialize()
563 for (chip=start_chip; chip<stop_chip; chip++) in cvmx_nand_initialize()
816 for (chip=0; chip<8; chip++) in cvmx_nand_get_active_chips()
846 if ((chip < 0) || (chip > 7)) in cvmx_nand_set_timing()
1040 cmd.chip_en.chip = chip; in __cvmx_nand_build_pre_cmd()
1245 if ((chip < 0) || (chip > 7)) in __cvmx_nand_low_level_read()
1336 if ((chip < 0) || (chip > 7)) in cvmx_nand_page_read()
1383 if ((chip < 0) || (chip > 7)) in cvmx_nand_page_write()
1466 if ((chip < 0) || (chip > 7)) in cvmx_nand_block_erase()
1536 if ((chip < 0) || (chip > 7)) in cvmx_nand_read_id()
[all …]
H A Dcvmx-nand.h192 uint64_t chip : 3; member
605 extern cvmx_nand_status_t cvmx_nand_page_write(int chip, uint64_t nand_address, uint64_t buffer_add…
616 extern cvmx_nand_status_t cvmx_nand_block_erase(int chip, uint64_t nand_address);
631 extern int cvmx_nand_read_id(int chip, uint64_t nand_address, uint64_t buffer_address, int buffer_l…
644 extern int cvmx_nand_read_param_page(int chip, uint64_t buffer_address, int buffer_length);
653 extern int cvmx_nand_get_status(int chip);
663 extern int cvmx_nand_get_page_size(int chip);
672 extern int cvmx_nand_get_oob_size(int chip);
681 extern int cvmx_nand_get_pages_per_block(int chip);
690 extern int cvmx_nand_get_blocks(int chip);
[all …]
/freebsd-13.1/sys/mips/atheros/
H A Dar71xx_setup.c101 chip = "7130"; in ar71xx_detect_sys_type()
106 chip = "7141"; in ar71xx_detect_sys_type()
118 chip = "7240"; in ar71xx_detect_sys_type()
125 chip = "7241"; in ar71xx_detect_sys_type()
132 chip = "7242"; in ar71xx_detect_sys_type()
157 chip = "9330"; in ar71xx_detect_sys_type()
164 chip = "9331"; in ar71xx_detect_sys_type()
172 chip = "9341"; in ar71xx_detect_sys_type()
180 chip = "9342"; in ar71xx_detect_sys_type()
188 chip = "9344"; in ar71xx_detect_sys_type()
[all …]
/freebsd-13.1/sys/dev/wbwd/
H A Dwbwd.c103 enum chips chip; member
129 enum chips chip; member
139 .chip = w83627s,
199 .chip = nct6775,
204 .chip = nct6776,
209 .chip = nct6102,
214 .chip = nct6779,
219 .chip = nct6791,
224 .chip = nct6792,
229 .chip = nct6793,
[all …]
/freebsd-13.1/sys/mips/atheros/ar531x/
H A Dar5315_setup.c78 char *chip = "????"; in ar5315_detect_sys_type() local
115 chip = "2315"; in ar5315_detect_sys_type()
119 chip = "2316"; in ar5315_detect_sys_type()
123 chip = "2317"; in ar5315_detect_sys_type()
127 chip = "2318"; in ar5315_detect_sys_type()
140 chip = "5311"; in ar5315_detect_sys_type()
144 chip = "5312"; in ar5315_detect_sys_type()
148 chip = "2313"; in ar5315_detect_sys_type()
153 sprintf(ar5315_sys_type, "Atheros AR%s rev %u", chip, rev); in ar5315_detect_sys_type()
/freebsd-13.1/sys/dev/ata/chipsets/
H A Data-acerlabs.c114 switch (ctlr->chip->cfg2) { in ata_ali_chipinit()
116 ctlr->channels = ctlr->chip->cfg1; in ata_ali_chipinit()
145 if (ctlr->chip->chiprev < 0xc7) in ata_ali_chipinit()
154 if (ctlr->chip->chiprev <= 0xc4) in ata_ali_chipinit()
180 if (ctlr->chip->cfg2 == ALI_SATA) { in ata_ali_chipdeinit()
204 if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7) in ata_ali_ch_attach()
207 if (ctlr->chip->chiprev <= 0xc4) { in ata_ali_ch_attach()
212 if (ctlr->chip->cfg2 & ALI_NEW) in ata_ali_ch_attach()
275 if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) { in ata_ali_reset()
310 if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7) { in ata_ali_setmode()
[all …]
H A Data-siliconimage.c113 switch (ctlr->chip->cfg1) { in ata_sii_chipinit()
124 if (ctlr->chip->cfg2 & SII_SETCLK) { in ata_sii_chipinit()
130 ctlr->chip->text); in ata_sii_chipinit()
134 if (ctlr->chip->cfg2 & SII_4CH) { in ata_sii_chipinit()
151 if (ctlr->chip->max_dma >= ATA_SA150) { in ata_sii_chipinit()
187 if (ctlr->chip->cfg2 & SII_INTR) in ata_cmd_ch_attach()
226 mode = min(mode, ctlr->chip->max_dma); in ata_cmd_setmode()
283 if (ctlr->chip->cfg2 & SII_BUG) { in ata_sii_ch_attach()
291 if (ctlr->chip->cfg2 & SII_SETCLK) in ata_sii_ch_attach()
365 mode = min(mode, ctlr->chip->max_dma); in ata_sii_setmode()
[all …]
H A Data-promise.c212 ctlr->chip = idx; in ata_promise_probe()
226 switch (ctlr->chip->cfg1) { in ata_promise_chipinit()
259 if (ctlr->chip->cfg2 == PR_SX4X) { in ata_promise_chipinit()
308 switch (ctlr->chip->cfg2) { in ata_promise_chipinit()
340 if ((ctlr->chip->cfg2 == PR_SATA2) || (ctlr->chip->cfg2 == PR_CMBO2)) in ata_promise_chipinit()
369 if (ctlr->chip->cfg1 == PR_NEW) { in ata_promise_ch_attach()
474 switch (ctlr->chip->cfg1) { in ata_promise_setmode()
505 if (ctlr->chip->cfg1 < PR_TX) in ata_promise_setmode()
569 if (ctlr->chip->cfg2 & PR_SX4X) { in ata_promise_mio_ch_attach()
622 switch (ctlr->chip->cfg2) { in ata_promise_mio_status()
[all …]
H A Data-via.c134 if (!(ctlr->chip = ata_find_chip(dev, ids, -99))) in ata_via_probe()
138 if (!(ctlr->chip = ata_match_chip(dev, new_ids))) in ata_via_probe()
156 if (ctlr->chip->cfg2 & VIASATA) { in ata_via_chipinit()
164 if (ctlr->chip->max_dma >= ATA_SA150) { in ata_via_chipinit()
173 if (ctlr->chip->cfg2 & VIABAR) { in ata_via_chipinit()
183 if (ctlr->chip->cfg2 & VIACLK) in ata_via_chipinit()
187 if (ctlr->chip->cfg2 & VIABUG) in ata_via_chipinit()
216 if (ctlr->chip->cfg2 & VIABAR) { in ata_via_ch_attach()
273 if (ctlr->chip->cfg2 & VIABAR) { in ata_via_ch_detach()
322 if ((ctlr->chip->cfg2 & VIABAR) && (ch->unit > 1)) { in ata_via_new_setmode()
[all …]
H A Data-highpoint.c105 ctlr->chip = idx; in ata_highpoint_probe()
118 if (ctlr->chip->cfg2 == HPT_OLD) { in ata_highpoint_chipinit()
131 if (ctlr->chip->cfg1 < HPT_372) in ata_highpoint_chipinit()
154 if (ctlr->chip->cfg1 == HPT_366) in ata_highpoint_ch_attach()
185 mode = min(mode, ctlr->chip->max_dma); in ata_highpoint_setmode()
194 timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4); in ata_highpoint_setmode()
206 if (ctlr->chip->cfg1 == HPT_374 && pci_get_function(parent) == 1) { in ata_highpoint_check_80pin()
H A Data-nvidia.c178 if (!(ctlr->chip = ata_match_chip(dev, ids))) in ata_nvidia_probe()
181 if ((ctlr->chip->cfg1 & NVAHCI) && in ata_nvidia_probe()
198 if (ctlr->chip->cfg1 & NVAHCI) { in ata_nvidia_chipinit()
201 } else if (ctlr->chip->max_dma >= ATA_SA150) { in ata_nvidia_chipinit()
209 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; in ata_nvidia_chipinit()
219 if (ctlr->chip->cfg1 & NVQ) { in ata_nvidia_chipinit()
288 int offset = ctlr->chip->cfg1 & NV4 ? 0x0440 : 0x0010; in ata_nvidia_status()
289 int shift = ch->unit << (ctlr->chip->cfg1 & NVQ ? 4 : 2); in ata_nvidia_status()
293 if (ctlr->chip->cfg1 & NVQ) in ata_nvidia_status()
303 if (ctlr->chip->cfg1 & NVQ) in ata_nvidia_status()
[all …]
H A Data-amd.c82 if (!(ctlr->chip = ata_match_chip(dev, ids))) in ata_amd_probe()
99 if (ctlr->chip->cfg1 & AMD_BUG) in ata_amd_chipinit()
123 mode = min(mode, ctlr->chip->max_dma); in ata_amd_setmode()
124 if (ctlr->chip->cfg1 & AMD_CABLE) { in ata_amd_setmode()
154 if (ctlr->chip->cfg1 & AMD_CABLE) in ata_amd_ch_attach()
H A Data-jmicron.c89 ctlr->chip = idx; in ata_jmicron_probe()
110 ctlr->channels = ctlr->chip->cfg2; in ata_jmicron_chipinit()
117 if (ctlr->chip->cfg1) { in ata_jmicron_chipinit()
128 ctlr->channels = ctlr->chip->cfg2; in ata_jmicron_chipinit()
150 mode = min(mode, ctlr->chip->max_dma); in ata_jmicron_setmode()
/freebsd-13.1/sys/contrib/device-tree/Bindings/mtd/
H A Dfsl-upm-nand.txt5 - reg : should specify localbus chip select and size used for the chip.
10 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
11 The corresponding address lines are used to select the chip.
13 (R/B#). For multi-chip devices, "n" GPIO definitions are required
17 - fsl,upm-wait-flags : add chip-dependent short delays after running the
20 - chip-delay : chip dependent delay for transferring data from array to
24 Each flash chip described may optionally contain additional sub-nodes
55 /* Multi-chip NAND device */
H A Djedec,spi-nor.txt7 manufacturer and name of the chip. A list of supported chip
12 Supported chip names:
50 The following chip names have been used historically to
64 - spi-max-frequency : Maximum frequency of the SPI bus the chip can operate at
67 - m25p,fast-read : Use the "fast read" opcode to read data from the chip instead
71 by your chip.
/freebsd-13.1/contrib/ofed/libcxgb4/
H A Dt4_chip_type.h70 static inline int is_t4(enum chip_type chip) in is_t4() argument
72 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4); in is_t4()
75 static inline int is_t5(enum chip_type chip) in is_t5() argument
77 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5); in is_t5()
80 static inline int is_t6(enum chip_type chip) in is_t6() argument
82 return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T6); in is_t6()
/freebsd-13.1/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,disp.txt29 - compatible: "mediatek,<chip>-disp-<function>", one of
32 "mediatek,<chip>-disp-rdma" - read DMA / line buffer
33 "mediatek,<chip>-disp-wdma" - write DMA
35 "mediatek,<chip>-disp-color" - color processor
36 "mediatek,<chip>-disp-dither" - dither
38 "mediatek,<chip>-disp-gamma" - gamma correction
44 "mediatek,<chip>-disp-mutex" - display mutex
45 "mediatek,<chip>-disp-od" - overdrive
59 "mediatek,<chip>-disp-ovl"
60 "mediatek,<chip>-disp-rdma"
[all …]
/freebsd-13.1/sys/contrib/device-tree/Bindings/input/touchscreen/
H A Dpixcir_i2c_ts.txt5 - reg: I2C address of the chip
6 - interrupts: interrupt to which the chip is connected
7 - attb-gpio: GPIO connected to the ATTB line of the chip
12 - reset-gpios: GPIO connected to the RESET line of the chip
13 - enable-gpios: GPIO connected to the ENABLE line of the chip
14 - wake-gpios: GPIO connected to the WAKE line of the chip
H A Dmelfas_mip4.txt5 - reg: I2C slave address of the chip (0x48 or 0x34)
6 - interrupts: interrupt to which the chip is connected
9 - ce-gpios: GPIO connected to the CE (chip enable) pin of the chip
/freebsd-13.1/sys/contrib/device-tree/Bindings/net/nfc/
H A Dnfcmrvl.txt12 - reset-n-io: Output GPIO pin used to reset the chip (active low).
13 - hci-muxed: Specifies that the chip is muxing NCI over HCI frames.
15 Optional UART-based chip specific properties:
16 - flow-control: Specifies that the chip is using RTS/CTS.
17 - break-control: Specifies that the chip needs specific break management.
19 Optional I2C-based chip specific properties:
20 - i2c-int-falling: Specifies that the chip read event shall be trigged on
22 - i2c-int-rising: Specifies that the chip read event shall be trigged on
/freebsd-13.1/sys/contrib/device-tree/Bindings/power/reset/
H A Dltc2952-poweroff.txt3 This chip is used to externally trigger a system shut down. Once the trigger has
4 been sent, the chip's watchdog has to be reset to gracefully shut down.
11 chip's watchdog line
13 chip's kill line
17 chip's trigger line. If this property is not set, the
18 trigger function is ignored and the chip is kept alive
/freebsd-13.1/sys/contrib/device-tree/Bindings/spi/
H A Dspi-sprd-adi.txt4 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
9 48 hardware channels to access analog chip. For 2 software read/write channels,
10 users should set ADI registers to access analog chip. For hardware channels,
12 which means we can just link one analog chip address to one hardware channel,
13 then users can access the mapped analog chip address by this hardware channel
19 the analog chip address where user want to access by hardware components.
21 Since we have multi-subsystems will use unique ADI to access analog chip, when
36 - #address-cells: Number of cells required to define a chip select address
38 - #size-cells: Size of cells required to define a chip select address size
48 value specifies the analog chip address where user want to access
/freebsd-13.1/sys/contrib/device-tree/Bindings/mips/cavium/
H A Dbootbus.txt3 The Octeon Boot Bus is a configurable parallel bus with 8 chip
4 selects. Each chip select is independently configurable.
13 - #address-cells: Must be <2>. The first cell is the chip select
14 within the bootbus. The second cell is the offset from the chip select.
19 parent-bus-address, length) for each active chip select. If the
20 length element for any triplet is zero, the chip select is disabled,
23 The configuration parameters for each chip select are stored in child
29 - cavium,cs-index: A single cell indicating the chip select that
60 the bus for this chip select.
72 /* The chip select number and offset */
[all …]
/freebsd-13.1/sys/mips/ingenic/
H A Djz4780_pinctrl.c66 #define CHIP_REG_OFFSET(base, chip) ((base) + (chip) * CHIP_REG_STRIDE) argument
191 device_t chip; in jz4780_pinctrl_configure_pins() local
213 chip = jz4780_pinctrl_chip_lookup(sc, pconf[0]); in jz4780_pinctrl_configure_pins()
214 if (chip == NULL) { in jz4780_pinctrl_configure_pins()
223 pconf[1], ofw_bus_get_name(chip)); in jz4780_pinctrl_configure_pins()
227 result = JZ4780_GPIO_CONFIGURE_PIN(chip, pconf[1], pconf[2], in jz4780_pinctrl_configure_pins()
232 ofw_bus_get_name(chip)); in jz4780_pinctrl_configure_pins()
/freebsd-13.1/sys/contrib/device-tree/Bindings/arm/freescale/
H A Dfsl,layerscape-scfg.txt4 configuration and status registers for the chip. Such as getting PEX port
8 - compatible: Should contain a chip-specific compatible string,
9 Chip-specific strings are of the form "fsl,<chip>-scfg",
10 The following <chip>s are known to be supported:

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