Searched refs:buildSExtInReg (Results 1 – 4 of 4) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 1178 B.buildSExtInReg(MI.getOperand(0), WideLoad, MemSize); in applyMappingLoad()
1666 auto ExtLo = B.buildSExtInReg(S32, Bitcast, 16); in unpackV2S16ToS32()
2478 B.buildSExtInReg(DstRegs[0], SrcRegs[0], Amt); in applyMappingImpl()
2485 B.buildSExtInReg(DstRegs[1], DstRegs[0], Amt - 32); in applyMappingImpl()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | MachineIRBuilder.h | 611 MachineInstrBuilder buildSExtInReg(const DstOp &Res, const SrcOp &Op, int64_t ImmOp) { in buildSExtInReg() function
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerHelper.cpp | 1948 ExtResult = MIRBuilder.buildSExtInReg(WideTy, Mul, SrcBitWidth); in widenScalarMulo()
2914 MIRBuilder.buildSExtInReg(LoadReg, NewLoad, MemSizeInBits); in lowerLoad()
4293 R = MIRBuilder.buildSExtInReg(NarrowTy, R, Imm).getReg(0); in fewerElementsVectorSextInReg()
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| H A D | CombinerHelper.cpp | 3047 Builder.buildSExtInReg(MI.getOperand(0).getReg(), Src, Size - ShiftAmt); in applyAshShlToSextInreg()
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