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Searched refs:buildBitcast (Results 1 – 7 of 7) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPreLegalizerCombiner.cpp143 auto Bitcast = B.buildBitcast({S32}, CvtPk); in applyClampI64ToI16()
H A DAMDGPURegisterBankInfo.cpp1663 auto Bitcast = B.buildBitcast(S32, Src); in unpackV2S16ToS32()
2127 B.buildBitcast(MI.getOperand(0).getReg(), Vec); in foldInsertEltToCmpSelect()
2659 B.buildBitcast(DstReg, Or); in applyMappingImpl()
2738 auto CastSrc = B.buildBitcast(Vec32, SrcReg); in applyMappingImpl()
2856 auto CastSrc = B.buildBitcast(Vec32, SrcReg); in applyMappingImpl()
2891 B.buildBitcast(DstReg, InsHi); in applyMappingImpl()
2908 B.buildBitcast(DstReg, InsHi); in applyMappingImpl()
H A DAMDGPULegalizerInfo.cpp2742 B.buildBitcast(Dst, Merge); in legalizeBuildVector()
3749 Reg = B.buildBitcast(S32, Reg).getReg(0); in handleD16VData()
3763 return B.buildBitcast(LLT::fixed_vector(3, S32), Reg).getReg(0); in handleD16VData()
3768 Reg = B.buildBitcast(LLT::fixed_vector(2, S32), Reg).getReg(0); in handleD16VData()
4174 AddrReg = B.buildBitcast(V2S16, AddrReg).getReg(0); in packImage16bitOpsToDwords()
4570 B.buildBitcast(DstReg, ResultRegs[0]); in legalizeImageIntrinsic()
4584 Reg = B.buildBitcast(V2S16, Reg).getReg(0); in legalizeImageIntrinsic()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp317 B.buildBitcast(OrigRegs[0], Regs[0]); in buildCopyFromRegs()
379 CastRegs[0] = B.buildBitcast(NewTy, Regs[0]).getReg(0); in buildCopyFromRegs()
393 CastRegs[I++] = B.buildBitcast(GCDTy, SrcReg).getReg(0); in buildCopyFromRegs()
H A DLegalizerHelper.cpp1335 return MIRBuilder.buildBitcast(NewTy, NewVal).getReg(0); in coerceToScalar()
1409 Op.setReg(MIRBuilder.buildBitcast(CastTy, Op).getReg(0)); in bitcastSrc()
1416 MIRBuilder.buildBitcast(MO, CastDst); in bitcastDst()
2629 SrcReg = MIRBuilder.buildBitcast(DstCastTy, SrcReg).getReg(0); in lowerBitcast()
2694 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); in bitcastExtractVectorElt()
2730 MIRBuilder.buildBitcast(Dst, NewVec); in bitcastExtractVectorElt()
2839 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); in bitcastInsertVectorElt()
2873 MIRBuilder.buildBitcast(Dst, InsertedElt); in bitcastInsertVectorElt()
4196 SrcReg = MIRBuilder.buildBitcast(SrcTy, SrcReg).getReg(0); in reduceOperationWidth()
4272 MIRBuilder.buildBitcast(DstRegs[I], MergeDstReg); in reduceOperationWidth()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1005 auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg); in legalizeLoadStore()
1009 MIRBuilder.buildBitcast(ValReg, NewLoad); in legalizeLoadStore()
1117 Val = MIRBuilder.buildBitcast(VTy, Val).getReg(0); in legalizeCTPOP()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h633 MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) { in buildBitcast() function