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Searched refs:bitsLT (Results 1 – 25 of 26) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DValueTypes.h273 bool bitsLT(EVT VT) const { in bitsLT() function
H A DTargetLowering.h4015 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp107 else if (Src.getValueType().bitsLT(MVT::i32)) in EmitSpecializedLibcall()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1143 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdownMVT()
1608 if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. in getVectorTypeBreakdown()
1671 if (VT.bitsLT(MinVT)) in GetReturnInfo()
H A DCodeGenPrepare.cpp1289 if (SrcVT.bitsLT(DstVT)) return false; in OptimizeNoopCopyExpression()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp2646 if (LegalSVT.bitsLT(SVT)) in getSplatValue()
4868 assert(Operand.getValueType().bitsLT(VT) && in getNode()
4895 assert(Operand.getValueType().bitsLT(VT) && in getNode()
4914 assert(Operand.getValueType().bitsLT(VT) && in getNode()
4933 assert(Operand.getValueType().bitsLT(VT) && in getNode()
4971 .bitsLT(VT.getScalarType())) in getNode()
5264 if (LegalSVT.bitsLT(SVT)) in FoldConstantArithmetic()
5388 if (LegalSVT.bitsLT(VT.getScalarType())) in FoldConstantVectorArithmetic()
6769 if (VT.bitsLT(LargestVT)) { in getMemsetStores()
8045 assert(Ops[1].getValueType().bitsLT(VTList.VTs[0]) && in getNode()
[all …]
H A DLegalizeTypesGeneric.cpp225 assert(OldEltVT.bitsLT(OldVT) && "Result type smaller then element type!"); in ExpandRes_EXTRACT_VECTOR_ELT()
H A DFastISel.cpp395 if (IdxVT.bitsLT(PtrVT)) { in getRegForGEPIndex()
1802 if (DstVT.bitsLT(SrcVT)) in selectOperator()
H A DLegalizeDAG.cpp1458 MemVT.bitsLT(Node->getOperand(0).getValueType()); in ExpandVectorBuildThroughStack()
2999 if (NewEltVT.bitsLT(EltVT)) { in ExpandNode()
4766 assert(NewEltVT.bitsLT(EltVT) && "not handled"); in PromoteNode()
4799 assert(NewEltVT.bitsLT(EltVT) && "not handled"); in PromoteNode()
4845 assert(NewEltVT.bitsLT(EltVT) && "not handled"); in PromoteNode()
H A DDAGCombiner.cpp5284 if (LdStMemVT.bitsLT(MemVT)) in isLegalNarrowLdSt()
11334 if (SrcVT.bitsLT(VT) && VT.isVector()) { in visitZERO_EXTEND()
11743 if (AssertVT.bitsLT(BigA_AssertVT)) { in visitAssertExt()
12023 ExtVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) in visitSIGN_EXTEND_INREG()
12224 if (N0.getOperand(0).getValueType().bitsLT(VT)) in visitTRUNCATE()
12375 if (LN0->isSimple() && LN0->getMemoryVT().bitsLT(VT)) { in visitTRUNCATE()
14865 if (VT.bitsLT(In.getValueType())) in visitFP_EXTEND()
18649 if (ResultVT.bitsLT(VecEltVT)) in scalarizeExtractedVectorLoad()
18895 if (ScalarVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, ScalarVT)) in visitEXTRACT_VECTOR_ELT()
21316 EVT ScaleVT = SVT.bitsLT(InnerSVT) ? VT : InnerVT; in visitVECTOR_SHUFFLE()
[all …]
H A DLegalizeVectorTypes.cpp500 if (BoolVT.bitsLT(CondVT)) in ScalarizeVecRes_VSELECT()
2188 if (N->getValueType(0).bitsLT( in SplitVectorOperand()
2487 if (N->getValueType(0).bitsLT(EltVT)) { in SplitVecOp_EXTRACT_VECTOR_ELT()
H A DSelectionDAGBuilder.cpp261 ValueVT.bitsLT(PartEVT)) { in getCopyFromParts()
274 if (ValueVT.bitsLT(PartEVT)) { in getCopyFromParts()
288 if (ValueVT.bitsLT(Val.getValueType())) in getCopyFromParts()
299 ValueVT.bitsLT(PartEVT)) { in getCopyFromParts()
438 } else if (ValueVT.bitsLT(PartEVT)) { in getCopyFromPartsVector()
H A DTargetLowering.cpp3876 else if (Op0.getValueType().bitsLT(VT)) in SimplifySetCC()
7927 if (VT.bitsLT(MVT::i32)) { in lowerCmpEqZeroToCtlzSrl()
8557 if (RType.bitsLT(Overflow.getValueType())) in expandMULO()
H A DLegalizeIntegerTypes.cpp4818 if (N->getOperand(i).getValueType().bitsLT(NOutVTElem)) in PromoteIntRes_BUILD_VECTOR()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1240 if (MemVT.bitsLT(MVT::i32)) in LowerSTORE()
1358 ExtType != ISD::NON_EXTLOAD && MemVT.bitsLT(MVT::i32)) { in LowerLOAD()
1584 if (VT.bitsLT(MVT::i32)) in allowsMisalignedMemoryAccesses()
H A DSIISelLowering.cpp1695 VT.bitsLT(MemVT)) { in convertArgType()
4925 if (NewVT.bitsLT(MVT::i32)) { in ReplaceNodeResults()
7977 if (VT.bitsLT(Op.getValueType())) in getLoadExtOrTrunc()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Support/
H A DMachineValueType.h1128 bool bitsLT(MVT VT) const { in bitsLT() function
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp1546 if (EltVT.bitsLT(XLenVT)) in selectVSplatSimmHelper()
H A DRISCVISelLowering.cpp2218 assert(DstEltVT.bitsLT(SrcEltVT) && in LowerOperation()
3511 if (OpVT.bitsLT(XLenVT)) { in lowerVectorIntrinsicSplats()
5310 if (VT.bitsLT(XLenVT)) { in ReplaceNodeResults()
6248 IndexVT.getVectorElementType().bitsLT(XLenVT)); in PerformDAGCombine()
6257 if (IndexVT.getVectorElementType().bitsLT(XLenVT)) { in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMips64InstrInfo.td71 return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLT(MVT::i32);
H A DMipsISelLowering.cpp4032 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp3631 if (DstVT.bitsLT(SrcVT)) in fastSelectInstruction()
H A DX86ISelLowering.cpp2937 return VT.bitsLT(MinVT) ? MinVT : VT; in getTypeForExtReturn()
22083 if (Sign.getSimpleValueType().bitsLT(VT)) in LowerFCOPYSIGN()
28305 else if (EltVT.bitsLT(MVT::i32)) in LowerScalarVariableShift()
49927 if (OutVT16.bitsLT(In0.getValueType())) { in matchPMADDWD_2()
49931 if (OutVT16.bitsLT(In1.getValueType())) { in matchPMADDWD_2()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp4877 if (IdxVT.bitsLT(PtrVT)) { in getRegForGEPIndex()
H A DAArch64ISelLowering.cpp7000 if (SrcVT.bitsLT(VT)) in LowerFCOPYSIGN()
8594 if (SrcEltTy.bitsLT(SmallestEltTy)) { in ReconstructShuffle()

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