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Searched refs:addDef (Results 1 – 25 of 44) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsInstructionSelector.cpp276 .addDef(Dest) in buildUnalignedLoad()
326 .addDef(PseudoMULTuReg) in select()
375 .addDef(JTIndex) in select()
392 .addDef(Dest) in select()
404 .addDef(Dest) in select()
482 .addDef(ImplDef); in select()
519 .addDef(HILOReg) in select()
577 .addDef(Dst); in select()
652 .addDef(ResultInFPR) in select()
873 .addDef(TrueInReg) in select()
[all …]
H A DMipsISelLowering.cpp4770 .addDef(Temp) in emitLDR_W()
4817 .addDef(Temp) in emitLDR_D()
4826 .addDef(Lo) in emitLDR_D()
4830 .addDef(Hi) in emitLDR_D()
4902 .addDef(Tmp) in emitSTR_W()
4914 .addDef(Tmp) in emitSTR_W()
4955 .addDef(Lo) in emitSTR_D()
4970 .addDef(Lo) in emitSTR_D()
4974 .addDef(Hi) in emitSTR_D()
4994 .addDef(Lo) in emitSTR_D()
[all …]
H A DMipsCallLowering.cpp120 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
465 MIB.addDef(Mips::SP, RegState::Implicit); in lowerCall()
526 MIB.addDef(Mips::GP, RegState::Implicit); in lowerCall()
H A DMipsSEISelDAGToDAG.cpp134 .addDef(Mips::AT_64) in emitMCountABI()
142 .addDef(Mips::AT) in emitMCountABI()
147 .addDef(Mips::SP) in emitMCountABI()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SpeculationHardening.cpp232 .addDef(MisspeculatingTaintReg) in insertTrackingCode()
370 .addDef(AArch64::XZR) in insertSPToRegTaintPropagation()
376 .addDef(MisspeculatingTaintReg) in insertSPToRegTaintPropagation()
393 .addDef(TmpReg) in insertRegToSPTaintPropagation()
399 .addDef(TmpReg, RegState::Renamable) in insertRegToSPTaintPropagation()
405 .addDef(AArch64::SP) in insertRegToSPTaintPropagation()
453 .addDef(Reg) in makeGPRSpeculationSafe()
577 .addDef(DstReg) in expandSpeculationSafeValue()
H A DAArch64LowerHomogeneousPrologEpilog.cpp211 MIB.addDef(AArch64::SP); in emitStore()
234 MIB.addDef(AArch64::SP); in emitLoad()
313 .addDef(AArch64::FP) in getOrCreateFrameHelper()
328 .addDef(AArch64::X16) in getOrCreateFrameHelper()
557 .addDef(AArch64::FP) in lowerProlog()
H A DAArch64ExpandPseudoInsts.cpp652 .addDef(AddressReg) in expandSetTagLoop()
659 .addDef(SizeReg) in expandSetTagLoop()
984 .addDef(Reg32) in expandMI()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp763 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu).addUse(VMZu); in expandPseudoLogM()
764 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl).addUse(VMZl); in expandPseudoLogM()
768 BuildMI(*MBB, MI, DL, MCID).addDef(VMXu).addUse(VMYu); in expandPseudoLogM()
769 BuildMI(*MBB, MI, DL, MCID).addDef(VMXl).addUse(VMYl); in expandPseudoLogM()
897 .addDef(VMX) in expandPostRAPseudo()
903 .addDef(VMX) in expandPostRAPseudo()
911 .addDef(VMX) in expandPostRAPseudo()
920 .addDef(VMX) in expandPostRAPseudo()
1070 .addDef(MI.getOperand(0).getReg()) in expandGetStackTopPseudo()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp495 .addDef(DestReg) in putConstant()
599 .addDef(ResReg) in insertComparison()
696 .addDef(ResultReg) in selectGlobal()
793 .addDef(ResReg) in selectSelect()
887 .addDef(SExtResult) in select()
936 .addDef(DstReg) in select()
937 .addDef(IgnoredBits) in select()
H A DARMLowOverheadLoops.cpp1420 MIB.addDef(ARM::LR); in RevertLoopEndDec()
1505 MIB.addDef(ARM::LR); in ExpandLoopStart()
1665 MIB.addDef(ARM::LR); in Expand()
H A DThumb1FrameLowering.cpp419 .addDef(ARM::CPSR) in emitPrologue()
425 .addDef(ARM::CPSR) in emitPrologue()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRRelaxMemOperations.cpp116 .addDef(Ptr.getReg(), getKillRegState(Ptr.isKill())); in relax()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp264 .addDef(getMRI()->createGenericVirtualRegister(EltTy)) in buildConstant()
297 .addDef(getMRI()->createGenericVirtualRegister(EltTy)) in buildFConstant()
719 MIB.addDef(ResultReg); in buildIntrinsic()
803 .addDef(OldValRes) in buildAtomicCmpXchgWithSuccess()
804 .addDef(SuccessRes) in buildAtomicCmpXchgWithSuccess()
829 .addDef(OldValRes) in buildAtomicCmpXchg()
956 return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA); in buildBlockAddress()
H A DRegBankSelect.cpp165 .addDef(Dst) in repairReg()
195 .addDef(MO.getReg()); in repairReg()
205 UnMergeBuilder.addDef(DefReg); in repairReg()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CallLowering.cpp228 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
345 .addDef(X86::AL) in lowerCall()
H A DX86InstructionSelector.cpp257 .addDef(ExtSrc) in selectCopy()
883 .addDef(DstReg) in selectAnyext()
1660 .addDef(DstReg) in selectDivRem()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegisterBankInfo.cpp662 .addDef(LoLHS) in split64BitValueForMapping()
663 .addDef(HiLHS) in split64BitValueForMapping()
788 .addDef(PhiExec) in executeInWaterfallLoop()
1005 .addDef(NewExec) in executeInWaterfallLoop()
1012 .addDef(ExecReg) in executeInWaterfallLoop()
1030 .addDef(ExecReg) in executeInWaterfallLoop()
1100 .addDef(SGPR) in constrainOpWithReadfirstlane()
1876 .addDef(DstReg) in buildVCopy()
1886 .addDef(TmpReg0) in buildVCopy()
1889 .addDef(TmpReg1) in buildVCopy()
[all …]
H A DAMDGPUInstructionSelector.cpp338 .addDef(UnusedCarry, RegState::Dead) in selectG_ADD_SUB()
372 .addDef(CarryReg) in selectG_ADD_SUB()
911 .addDef(Dst1) in selectDivScale()
1691 MIB.addDef(TmpReg); in selectImageIntrinsic()
1698 MIB.addDef(VDataOut); // vdata output in selectImageIntrinsic()
4002 .addDef(RSrc2) in buildRSRC()
4005 .addDef(RSrc3) in buildRSRC()
4012 .addDef(RSrcHi) in buildRSRC()
4022 .addDef(RSrcLo) in buildRSRC()
4027 .addDef(RSrc) in buildRSRC()
[all …]
H A DSIShrinkInstructions.cpp567 .addDef(X1.Reg, 0, X1.SubReg) in matchSwap()
568 .addDef(Y1.Reg, 0, Y1.SubReg) in matchSwap()
H A DAMDGPULegalizerInfo.cpp1797 .addDef(GetReg) in getSegmentAperture()
2335 .addDef(PCReg); in buildPCRelGlobalAddress()
2588 .addDef(DstReg) in legalizeAtomicCmpXChg()
3976 .addDef(LoadDstReg) // vdata in legalizeBufferLoad()
4017 .addDef(MI.getOperand(0).getReg()) in legalizeAtomicIncDec()
4132 MIB.addDef(Dst); in legalizeBufferAtomic()
4817 .addDef(DstReg) in legalizeBVHIntrinsic()
4861 .addDef(Def) in legalizeIntrinsic()
4866 .addDef(Def) in legalizeIntrinsic()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DMachineIRBuilder.h76 MIB.addDef(Reg); in addDefToMIB()
79 MIB.addDef(MRI.createGenericVirtualRegister(LLTTy)); in addDefToMIB()
82 MIB.addDef(MRI.createVirtualRegister(RC)); in addDefToMIB()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp796 .addDef(Hexagon::D15) in insertEpilogueInBlock()
846 .addDef(Hexagon::D15) in insertEpilogueInBlock()
852 .addDef(Hexagon::D15) in insertEpilogueInBlock()
873 .addDef(Hexagon::D15) in insertEpilogueInBlock()
904 .addDef(SP) in insertAllocframe()
916 .addDef(SP) in insertAllocframe()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp209 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
1138 MIB.addDef(AArch64::X21, RegState::Implicit); in lowerCall()
H A DAArch64InstructionSelector.cpp1850 .addDef(ArgsAddrReg) in selectVaStartDarwin()
1886 auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg); in materializeLargeCMVal()
2648 .addDef(SrcReg) in select()
2772 IsStore ? NewInst.addUse(ValReg) : NewInst.addDef(ValReg); in select()
3044 .addDef(ExtSrc) in select()
3458 .addDef(AArch64::X0, RegState::Implicit) in selectTLSGlobalValue()
3819 .addDef(SubToRegDef) in selectMergeValues()
3827 .addDef(SubToRegDef2) in selectMergeValues()
3833 .addDef(I.getOperand(0).getReg()) in selectMergeValues()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveDebugVariables.cpp417 void addDef(SlotIndex Idx, ArrayRef<MachineOperand> LocMOs, bool IsIndirect, in addDef() function in __anonef106bf80411::UserValue
865 UV->addDef(Idx, in handleDebugValue()
876 UV->addDef(Idx, UndefMOs, false, IsList, *Expr); in handleDebugValue()

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