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Searched refs:XLenVT (Results 1 – 15 of 15) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp116 MVT XLenVT = Subtarget.getXLenVT(); in selectImm() local
227 MVT XLenVT = Subtarget->getXLenVT(); in addVectorLoadStoreOperands() local
281 MVT XLenVT = Subtarget->getXLenVT(); in selectVLSEGFF() local
449 MVT XLenVT = Subtarget->getXLenVT(); in Select() local
456 if (VT == XLenVT && ConstNode->isNullValue()) { in Select()
583 RISCV::SLLI, DL, XLenVT, X, in Select()
613 RISCV::SLLI, DL, XLenVT, X, in Select()
637 if (Src2.getValueType() != XLenVT) in Select()
706 if (Src2.getValueType() != XLenVT) in Select()
1542 MVT XLenVT = Subtarget.getXLenVT(); in selectVSplatSimmHelper() local
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H A DRISCVISelLowering.cpp81 MVT XLenVT = Subtarget.getXLenVT(); in RISCVTargetLowering() local
3422 DAG.getNode(ISD::ADD, DL, XLenVT, Idx, DAG.getConstant(1, DL, XLenVT)); in lowerINSERT_VECTOR_ELT()
3511 if (OpVT.bitsLT(XLenVT)) { in lowerVectorIntrinsicSplats()
3675 DAG.getNode(ISD::SHL, DL, XLenVT, VL, DAG.getConstant(1, DL, XLenVT)); in LowerINTRINSIC_WO_CHAIN()
4262 DAG.getNode(ISD::SUB, DL, XLenVT, VLMax, DAG.getConstant(1, DL, XLenVT)); in lowerVECTOR_REVERSE()
4774 DAG.getNode(ISD::SHL, DL, XLenVT, RM, DAG.getConstant(2, DL, XLenVT)); in lowerGET_ROUNDING()
5156 DAG.getNode(Opc, DL, XLenVT, NewOp0, DAG.getConstant(Imm, DL, XLenVT)); in ReplaceNodeResults()
5310 if (VT.bitsLT(XLenVT)) { in ReplaceNodeResults()
7120 LocVT = XLenVT; in CC_RISCV()
7182 LocVT = XLenVT; in CC_RISCV()
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H A DRISCVInstrInfoVVLPatterns.td26 SDTCisVT<2, XLenVT>]>;
28 SDTCisVT<2, XLenVT>]>;
35 SDTCisVT<4, XLenVT>]>;
41 SDTCisVT<3, XLenVT>]>;
47 SDTCisVT<4, XLenVT>]>;
115 SDTCisVT<5, XLenVT>]>;
197 def true_mask : PatLeaf<(riscv_vmset_vl (XLenVT srcvalue))>;
229 SDTCisVT<4, XLenVT>]>;
235 SDTCisSameNumEltsAs<1, 3>, SDTCisVT<4, XLenVT>
914 def : Pat<(vti.Vector (riscv_vmv_v_x_vl (ImmPat XLenVT:$imm5),
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H A DRISCVInstrInfoC.td21 def uimmlog2xlennonzero : Operand<XLenVT>, ImmLeaf<XLenVT, [{
39 def simm6 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<6>(Imm);}]> {
51 def simm6nonzero : Operand<XLenVT>,
64 def immzero : Operand<XLenVT>,
81 def c_lui_imm : Operand<XLenVT>,
98 def uimm7_lsb00 : Operand<XLenVT>,
112 def uimm8_lsb00 : Operand<XLenVT>,
126 def uimm8_lsb000 : Operand<XLenVT>,
157 def uimm9_lsb000 : Operand<XLenVT>,
173 ImmLeaf<XLenVT,
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H A DRISCVInstrInfo.td121 def fencearg : Operand<XLenVT> {
135 def uimmlog2xlen : Operand<XLenVT>, ImmLeaf<XLenVT, [{
155 def uimm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]> {
162 def simm12 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<12>(Imm);}]> {
238 def bare_symbol : Operand<XLenVT> {
250 def call_symbol : Operand<XLenVT> {
284 def csr_sysreg : Operand<XLenVT> {
293 def ixlenimm : Operand<XLenVT>;
302 def simm12_plus1 : ImmLeaf<XLenVT,
306 def uimm6gt32 : ImmLeaf<XLenVT, [{
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H A DRISCVInstrInfoB.td47 def shfl_uimm : Operand<XLenVT>, ImmLeaf<XLenVT, [{
77 def BCLRMask : ImmLeaf<XLenVT, [{
84 def BSETINVMask : ImmLeaf<XLenVT, [{
972 def : Pat<(or (and (shl GPR:$rs2, (XLenVT 8)), 0xFFFF),
982 def non_imm12 : PatLeaf<(XLenVT GPR:$a), [{
988 def : Pat<(add (shl GPR:$rs1, (XLenVT 1)), non_imm12:$rs2),
990 def : Pat<(add (shl GPR:$rs1, (XLenVT 2)), non_imm12:$rs2),
992 def : Pat<(add (shl GPR:$rs1, (XLenVT 3)), non_imm12:$rs2),
995 def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 6)), GPR:$rs2),
997 def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 10)), GPR:$rs2),
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H A DRISCVSubtarget.h64 MVT XLenVT = MVT::i32; variable
131 MVT getXLenVT() const { return XLenVT; } in getXLenVT()
H A DRISCVRegisterInfo.td118 def XLenVT : ValueTypeByHwMode<[RV32, RV64],
126 def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add
137 def GPRX0 : RegisterClass<"RISCV", [XLenVT], 32, (add X0)> {
143 def GPRNoX0 : RegisterClass<"RISCV", [XLenVT], 32, (add
154 def GPRNoX0X2 : RegisterClass<"RISCV", [XLenVT], 32, (add
169 def GPRJALR : RegisterClass<"RISCV", [XLenVT], 32, (add
179 def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add
190 def GPRTC : RegisterClass<"RISCV", [XLenVT], 32, (add
198 def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> {
H A DRISCVSubtarget.cpp67 XLenVT = MVT::i64; in initializeSubtargetDependencies()
H A DRISCVInstrInfoVSDPatterns.td32 SDTCisVT<1, XLenVT>]>;
37 (xor node:$in, (riscv_vmset_vl (XLenVT srcvalue)))>;
435 (vti.Vector (splat_vector (XLenVT 1)))),
441 (vti.Vector (rv32_splat_i64 (XLenVT 1)))),
509 (mul_oneuse (SplatPat XLenVT:$rs1),
515 (mul_oneuse (SplatPat XLenVT:$rs1),
530 def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), (SplatPat XLenVT:$rs1),
H A DRISCVInstrInfoVPseudos.td36 def VLOp : ComplexPattern<XLenVT, 1, "selectVLOp">;
137 def VLOpFrag : PatFrag<(ops), (XLenVT (VLOp (XLenVT AVL:$vl)))>;
140 def VLMax : OutPatFrag<(ops), (XLenVT X0)>;
171 string ScalarSuffix = !cond(!eq(Scal, XLenVT) : "X",
178 VReg Reg, LMULInfo M, ValueType Scal = XLenVT,
2467 def : Pat<(XLenVT (!cast<Intrinsic>(intrinsic_name)
2554 (XLenVT (VLOp (XLenVT (XLenVT GPR:$vl)))))),
2853 vti.Vector, XLenVT, vti.Mask,
2869 vti.Mask, vti.Vector, XLenVT,
2877 vti.Mask, vti.Vector, XLenVT,
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H A DRISCVInstrInfoZfh.td21 : SDTypeProfile<1, 1, [SDTCisVT<0, f16>, SDTCisVT<1, XLenVT>]>;
23 : SDTypeProfile<1, 1, [SDTCisVT<0, XLenVT>, SDTCisVT<1, f16>]>;
H A DRISCVInstrInfoV.td28 def VTypeIOp : Operand<XLenVT> {
51 def simm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> {
69 def simm5_plus1 : Operand<XLenVT>, ImmLeaf<XLenVT,
H A DRISCVInstrInfoA.td65 ValueType vt = XLenVT> {
H A DRISCVInstrInfoF.td46 def frmarg : Operand<XLenVT> {