| /freebsd-13.1/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/ |
| H A D | RegisterFile.cpp | 415 if (Writes.size() != Reads.size()) in tryEliminateMoveOrSwap()
422 if (Writes.empty() || Writes.size() > 2) in tryEliminateMoveOrSwap()
491 SmallVectorImpl<WriteRef> &Writes, in collectWrites() argument
508 Writes.push_back(WR); in collectWrites()
523 Writes.push_back(WR); in collectWrites()
536 if (Writes.size() > 1) { in collectWrites()
540 auto It = std::unique(Writes.begin(), Writes.end()); in collectWrites()
541 Writes.resize(std::distance(Writes.begin(), It)); in collectWrites()
558 SmallVector<WriteRef, 4> Writes; in checkRAWHazards() local
566 for (const WriteRef &WR : Writes) { in checkRAWHazards()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleA57.td | 67 list <SchedWriteRes> Writes = writes;
827 SchedVar<A57LMAddrPred1, A57VLDMOpsListUncond.Writes[0-1]>,
828 SchedVar<A57LMAddrPred2, A57VLDMOpsListUncond.Writes[0-3]>,
847 SchedVar<A57LMAddrPred1, A57VLDMOpsListCond.Writes[0-1]>,
848 SchedVar<A57LMAddrPred2, A57VLDMOpsListCond.Writes[0-3]>,
849 SchedVar<A57LMAddrPred3, A57VLDMOpsListCond.Writes[0-5]>,
850 SchedVar<A57LMAddrPred4, A57VLDMOpsListCond.Writes[0-7]>,
851 SchedVar<A57LMAddrPred5, A57VLDMOpsListCond.Writes[0-9]>,
852 SchedVar<A57LMAddrPred6, A57VLDMOpsListCond.Writes[0-11]>,
853 SchedVar<A57LMAddrPred7, A57VLDMOpsListCond.Writes[0-13]>,
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| H A D | ARMScheduleA9.td | 1882 list <WriteSequence> Writes = writes;
2110 SchedVar<A9LMAdr1Pred, A9WriteLMOpsList.Writes[0-1]>,
2111 SchedVar<A9LMAdr2Pred, A9WriteLMOpsList.Writes[0-3]>,
2112 SchedVar<A9LMAdr3Pred, A9WriteLMOpsList.Writes[0-5]>,
2113 SchedVar<A9LMAdr4Pred, A9WriteLMOpsList.Writes[0-7]>,
2114 SchedVar<A9LMAdr5Pred, A9WriteLMOpsList.Writes[0-9]>,
2115 SchedVar<A9LMAdr6Pred, A9WriteLMOpsList.Writes[0-11]>,
2116 SchedVar<A9LMAdr7Pred, A9WriteLMOpsList.Writes[0-13]>,
2117 SchedVar<A9LMAdr8Pred, A9WriteLMOpsList.Writes[0-15]>,
2215 SchedVar<A9LMAdr1Pred, A9WriteLMfpPostRAOpsList.Writes[0-0, 8-8]>,
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| H A D | ARMParallelDSP.cpp | 344 SmallVector<Instruction*, 8> Writes; in RecordMemoryOps() local
353 Writes.push_back(&I); in RecordMemoryOps()
370 for (auto Write : Writes) { in RecordMemoryOps()
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| /freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeGenSchedule.cpp | 874 IdxVec Writes, Reads; in collectSchedClasses() local
920 if (!SC.Writes.empty()) { in collectSchedClasses()
938 IdxVec Writes; in collectSchedClasses() local
941 Writes, Reads); in collectSchedClasses()
1030 SC.Writes = OperWrites; in addSchedClass()
1109 SC.Writes = SchedClasses[OldSCIdx].Writes; in createInstRWClass()
1256 IdxVec Writes, Reads; in inferFromItinClass() local
1278 IdxVec Writes, Reads; in inferFromInstRWs() local
1892 IdxVec Writes, Reads; in collectProcResources() local
1999 if (!SC.Writes.empty()) in checkCompleteness()
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| H A D | CodeGenSchedule.h | 132 IdxVec Writes; member
152 return ItinClassDef == IC && makeArrayRef(Writes) == W && in isKeyEqual()
562 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
638 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
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| H A D | SubtargetEmitter.cpp | 1023 IdxVec Writes = SC.Writes; in GenSchedClassTables() local
1037 Writes.clear(); in GenSchedClassTables()
1040 Writes, Reads); in GenSchedClassTables()
1043 if (Writes.empty()) { in GenSchedClassTables()
1049 Writes, Reads); in GenSchedClassTables()
1053 if (Writes.empty()) { in GenSchedClassTables()
1065 for (unsigned W : Writes) { in GenSchedClassTables()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/MC/ |
| H A D | MCInstrAnalysis.cpp | 21 APInt &Writes) const { in clearsSuperRegisters()
22 Writes.clearAllBits(); in clearsSuperRegisters()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/MCA/ |
| H A D | InstrBuilder.cpp | 348 ID.Writes.resize(TotalDefs + NumVariadicOps); in populateWrites()
365 WriteDescriptor &Write = ID.Writes[CurrentDef]; in populateWrites()
392 WriteDescriptor &Write = ID.Writes[Index]; in populateWrites()
419 WriteDescriptor &Write = ID.Writes[NumExplicitDefs + NumImplicitDefs]; in populateWrites()
443 WriteDescriptor &Write = ID.Writes[CurrentDef]; in populateWrites()
457 ID.Writes.resize(CurrentDef); in populateWrites()
709 if (D.Writes.empty()) in createInstruction()
714 APInt WriteMask(D.Writes.size(), 0); in createInstruction()
723 for (const WriteDescriptor &WD : D.Writes) { in createInstruction()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LoopDataPrefetch.cpp | 237 bool Writes; member
243 : LSCEVAddRec(L), InsertPt(nullptr), Writes(false), MemI(nullptr) { in Prefetch()
256 Writes = isa<StoreInst>(I); in addInstruction()
267 Writes = true; in addInstruction()
406 ConstantInt::get(I32, P.Writes), in runOnLoop()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CalcSpillWeights.cpp | 253 bool Reads, Writes; in weightCalcHelper() local
254 std::tie(Reads, Writes) = MI->readsWritesVirtualRegister(LI.reg()); in weightCalcHelper()
255 Weight = LiveIntervals::getSpillWeight(Writes, Reads, &MBFI, *MI); in weightCalcHelper()
258 if (Writes && IsExiting && LIS.isLiveOutOfMBB(LI, MBB)) in weightCalcHelper()
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| H A D | MachineInstrBundle.cpp | 300 RI.Writes = true; in AnalyzeVirtRegInBundle()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MCA/HardwareUnits/ |
| H A D | RegisterFile.h | 237 SmallVectorImpl<WriteRef> &Writes,
278 bool tryEliminateMoveOrSwap(MutableArrayRef<WriteState> Writes,
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MCA/ |
| H A D | Instruction.h | 376 void setDependentWrites(unsigned Writes) { in setDependentWrites() argument
377 DependentWrites = Writes; in setDependentWrites()
378 IsReady = !Writes; in setDependentWrites()
448 SmallVector<WriteDescriptor, 2> Writes; // Implicit writes are at the end. member
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrAnalysis.h | 88 APInt &Writes) const;
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IntrinsicsARM.td | 96 // Writes to the GE bits.
103 // Writes to the GE bits.
106 // Writes to the GE bits.
117 // Writes to the GE bits.
137 // Writes to the GE bits.
140 // Writes to the GE bits.
151 // Writes to the GE bits.
154 // Writes to the GE bits.
157 // Writes to the GE bits.
160 // Writes to the GE bits.
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| /freebsd-13.1/contrib/llvm-project/lld/docs/ |
| H A D | AtomLLD.rst | 14 * Writes standard Executable Files
|
| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBundle.h | 224 bool Writes; member
|
| /freebsd-13.1/crypto/openssl/doc/man1/ |
| H A D | rand.pod | 54 Writes random data to the specified I<file> upon exit.
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| H A D | gendsa.pod | 64 Writes random data to the specified I<file> upon exit.
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| H A D | passwd.pod | 102 Writes random data to the specified I<file> upon exit.
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| H A D | speed.pod | 72 Writes random data to the specified I<file> upon exit.
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| H A D | dsaparam.pod | 89 Writes random data to the specified I<file> upon exit.
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| H A D | genrsa.pod | 77 Writes random data to the specified I<file> upon exit.
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| /freebsd-13.1/sys/dev/ath/ath_hal/ar9001/ |
| H A D | ar9160.ini | 19 /* Auto Generated PCI Register Writes. Created: 05/22/08 */
633 /* Auto generated PCI Register Writes for SOWL1.0 ADDAC Shift Chain */
669 /* Auto generated PCI Register Writes for SOWL1.1 ADDAC Shift Chain */
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