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Searched refs:WriteRes (Results 1 – 25 of 48) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedRocket.td47 def : WriteRes<WriteJmp, [RocketUnitB]>;
48 def : WriteRes<WriteJal, [RocketUnitB]>;
49 def : WriteRes<WriteJalr, [RocketUnitB]>;
50 def : WriteRes<WriteJmpReg, [RocketUnitB]>;
78 def : WriteRes<WriteSTB, [RocketUnitMem]>;
79 def : WriteRes<WriteSTH, [RocketUnitMem]>;
80 def : WriteRes<WriteSTW, [RocketUnitMem]>;
81 def : WriteRes<WriteSTD, [RocketUnitMem]>;
86 def : WriteRes<WriteLDB, [RocketUnitMem]>;
170 def : WriteRes<WriteCSR, []>;
[all …]
H A DRISCVSchedSiFive7.td39 def : WriteRes<WriteJmp, [SiFive7PipeB]>;
40 def : WriteRes<WriteJal, [SiFive7PipeB]>;
41 def : WriteRes<WriteJalr, [SiFive7PipeB]>;
71 def : WriteRes<WriteSTB, [SiFive7PipeA]>;
72 def : WriteRes<WriteSTH, [SiFive7PipeA]>;
73 def : WriteRes<WriteSTW, [SiFive7PipeA]>;
74 def : WriteRes<WriteSTD, [SiFive7PipeA]>;
79 def : WriteRes<WriteLDB, [SiFive7PipeA]>;
80 def : WriteRes<WriteLDH, [SiFive7PipeA]>;
81 def : WriteRes<WriteLDW, [SiFive7PipeA]>;
[all …]
H A DRISCVScheduleV.td483 def : WriteRes<WriteVLDE8, []>;
487 def : WriteRes<WriteVSTE8, []>;
491 def : WriteRes<WriteVLDM, []>;
492 def : WriteRes<WriteVSTM, []>;
493 def : WriteRes<WriteVLDS8, []>;
497 def : WriteRes<WriteVSTS8, []>;
537 def : WriteRes<WriteVST1R, []>;
538 def : WriteRes<WriteVST2R, []>;
539 def : WriteRes<WriteVST4R, []>;
540 def : WriteRes<WriteVST8R, []>;
[all …]
H A DRISCVScheduleB.td53 def : WriteRes<WriteSHXADD, []>;
54 def : WriteRes<WriteSHXADD32, []>;
63 def : WriteRes<WriteRotateImm, []>;
67 def : WriteRes<WriteCLZ, []>;
68 def : WriteRes<WriteCLZ32, []>;
69 def : WriteRes<WriteCTZ, []>;
70 def : WriteRes<WriteCTZ32, []>;
71 def : WriteRes<WriteCPOP, []>;
72 def : WriteRes<WriteCPOP32, []>;
73 def : WriteRes<WriteREV8, []>;
[all …]
H A DRISCVSchedule.td187 def : WriteRes<WriteFALU16, []>;
188 def : WriteRes<WriteFClass16, []>;
197 def : WriteRes<WriteFDiv16, []>;
198 def : WriteRes<WriteFCmp16, []>;
199 def : WriteRes<WriteFLD16, []>;
200 def : WriteRes<WriteFMA16, []>;
201 def : WriteRes<WriteFMinMax16, []>;
202 def : WriteRes<WriteFMul16, []>;
205 def : WriteRes<WriteFSGNJ16, []>;
206 def : WriteRes<WriteFST16, []>;
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td70 def : WriteRes<WriteImm, []> { let Unsupported = 1; }
71 def : WriteRes<WriteI, []> { let Unsupported = 1; }
72 def : WriteRes<WriteISReg, []> { let Unsupported = 1; }
73 def : WriteRes<WriteIEReg, []> { let Unsupported = 1; }
74 def : WriteRes<WriteExtr, []> { let Unsupported = 1; }
75 def : WriteRes<WriteIS, []> { let Unsupported = 1; }
76 def : WriteRes<WriteID32, []> { let Unsupported = 1; }
77 def : WriteRes<WriteID64, []> { let Unsupported = 1; }
78 def : WriteRes<WriteIM32, []> { let Unsupported = 1; }
79 def : WriteRes<WriteIM64, []> { let Unsupported = 1; }
[all …]
H A DAArch64SchedKryo.td67 def : WriteRes<WriteISReg, [KryoUnitXY, KryoUnitXY]>
69 def : WriteRes<WriteIEReg, [KryoUnitXY, KryoUnitXY]>
71 def : WriteRes<WriteExtr, [KryoUnitXY, KryoUnitX]>
74 def : WriteRes<WriteID32, [KryoUnitXA, KryoUnitY]>
76 def : WriteRes<WriteID64, [KryoUnitXA, KryoUnitY]>
88 def : WriteRes<WriteF, [KryoUnitXY, KryoUnitXY]>
94 def : WriteRes<WriteFMul, [KryoUnitX, KryoUnitX]>
96 def : WriteRes<WriteFDiv, [KryoUnitXA, KryoUnitY]>
102 def : WriteRes<WriteSys, []> { let Latency = 1; }
103 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
[all …]
H A DAArch64SchedThunderX.td59 def : WriteRes<WriteIM32, [THXT8XUnitMAC]> {
64 def : WriteRes<WriteIM64, [THXT8XUnitMAC]> {
70 def : WriteRes<WriteID32, [THXT8XUnitDiv]> {
75 def : WriteRes<WriteID64, [THXT8XUnitDiv]> {
86 def : WriteRes<WriteVLD, [THXT8XUnitLdSt]> {
126 def : WriteRes<WriteVST, [THXT8XUnitLdSt]>;
142 def : WriteRes<WriteBr, [THXT8XUnitBr]>;
144 def : WriteRes<WriteBrReg, [THXT8XUnitBr]>;
147 def : WriteRes<WriteSys, [THXT8XUnitBr]>;
148 def : WriteRes<WriteBarrier, [THXT8XUnitBr]>;
[all …]
H A DAArch64SchedA53.td60 def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 3; }
61 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
64 def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 2; }
84 def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 6;
98 def : WriteRes<WriteAdr, []> { let Latency = 0; }
115 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
118 def : WriteRes<WriteBr, [A53UnitB]>;
119 def : WriteRes<WriteBrReg, [A53UnitB]>;
120 def : WriteRes<WriteSys, [A53UnitB]>;
121 def : WriteRes<WriteBarrier, [A53UnitB]>;
[all …]
H A DAArch64SchedA55.td75 def : WriteRes<WriteID32, [CortexA55UnitDiv]> {
78 def : WriteRes<WriteID64, [CortexA55UnitDiv]> {
83 def : WriteRes<WriteLD, [CortexA55UnitLd]> { let Latency = 3; }
90 def : WriteRes<WriteVLD, [CortexA55UnitLd]> { let Latency = 6;
114 def : WriteRes<WriteAdr, []> { let Latency = 0; }
135 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
138 def : WriteRes<WriteBr, [CortexA55UnitB]>;
139 def : WriteRes<WriteBrReg, [CortexA55UnitB]>;
140 def : WriteRes<WriteSys, [CortexA55UnitB]>;
141 def : WriteRes<WriteBarrier, [CortexA55UnitB]>;
[all …]
H A DAArch64SchedTSV110.td62 def : WriteRes<WriteID32, [TSV110UnitMDU]> { let Latency = 12;
64 def : WriteRes<WriteID64, [TSV110UnitMDU]> { let Latency = 20;
72 def : WriteRes<WriteLDHi, []> { let Latency = 4; }
83 def : WriteRes<WriteF, [TSV110UnitF]> { let Latency = 2; }
84 def : WriteRes<WriteFCmp, [TSV110UnitF]> { let Latency = 3; }
86 def : WriteRes<WriteFCopy, [TSV110UnitF]> { let Latency = 2; }
88 def : WriteRes<WriteFMul, [TSV110UnitF]> { let Latency = 5; }
100 def : WriteRes<WriteSys, []> { let Latency = 1; }
101 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
102 def : WriteRes<WriteHint, []> { let Latency = 1; }
[all …]
H A DAArch64SchedCyclone.td133 def : WriteRes<WriteImm, [CyUnitI]>;
152 def : WriteRes<WriteI, [CyUnitI]>;
158 def : WriteRes<WriteISReg, [CyUnitIS]> {
166 def : WriteRes<WriteIEReg, [CyUnitIS]> {
173 def : WriteRes<WriteIS, [CyUnitIS]>;
194 def : WriteRes<WriteIM32, [CyUnitIM]> {
198 def : WriteRes<WriteIM64, [CyUnitIM]> {
226 def : WriteRes<WriteLD, [CyUnitLS]> {
236 def : WriteRes<WriteST, [CyUnitLS]> {
267 def : WriteRes<WriteAdr, [CyUnitI]>;
[all …]
H A DAArch64SchedExynosM3.td207 def : WriteRes<WriteID32, [M3UnitC,
210 def : WriteRes<WriteID64, [M3UnitC,
213 def : WriteRes<WriteIM32, [M3UnitC]> { let Latency = 3; }
214 def : WriteRes<WriteIM64, [M3UnitC]> { let Latency = 4;
226 def : WriteRes<WriteLDHi, []> { let Latency = 4;
252 def : WriteRes<WriteVST, [M3UnitS,
257 def : WriteRes<WriteV, [M3UnitNALU]> { let Latency = 3; }
260 def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
261 def : WriteRes<WriteBarrier, []> { let Latency = 1; }
262 def : WriteRes<WriteHint, []> { let Latency = 1; }
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ScheduleSLM.td67 def : WriteRes<SchedRW, ExePorts> {
84 def : WriteRes<WriteRMW, [SLM_MEC_RSV]>;
89 def : WriteRes<WriteMove, [SLM_IEC_RSV01]>;
90 def : WriteRes<WriteZero, []>;
114 def : WriteRes<WriteIMulH, [SLM_FPC_RSV0]>;
137 def : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;
153 def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>;
185 def : WriteRes<WriteFStore, [SLM_MEC_RSV]>;
409 def : WriteRes<WriteVecExtract, [SLM_FPC_RSV0]>;
457 def : WriteRes<WriteFence, [SLM_MEC_RSV]>;
[all …]
H A DX86ScheduleAtom.td61 def : WriteRes<SchedRW, RRPorts> {
67 def : WriteRes<SchedRW.Folded, RMPorts> {
74 def : WriteRes<WriteRMW, [AtomPort0]>;
115 def : WriteRes<WriteSETCC, [AtomPort01]>;
132 def : WriteRes<WriteLEA, [AtomPort1]>;
164 def : WriteRes<WriteLoad, [AtomPort0]>;
165 def : WriteRes<WriteStore, [AtomPort0]>;
166 def : WriteRes<WriteStoreNT, [AtomPort0]>;
167 def : WriteRes<WriteMove, [AtomPort01]>;
178 def : WriteRes<WriteZero, []>;
[all …]
H A DX86SchedSandyBridge.td91 def : WriteRes<SchedRW, ExePorts> {
108 def : WriteRes<WriteRMW, [SBPort23,SBPort4]>;
113 def : WriteRes<WriteMove, [SBPort015]>;
114 def : WriteRes<WriteZero, []>;
182 def : WriteRes<WriteLEA, [SBPort01]>;
471 def : WriteRes<WritePCmpIStrM, [SBPort0]> {
483 def : WriteRes<WritePCmpEStrM, [SBPort015]> {
493 def : WriteRes<WritePCmpIStrI, [SBPort0]> {
532 def : WriteRes<WriteAESIMC, [SBPort5]> {
553 def : WriteRes<WriteCLMul, [SBPort015]> {
[all …]
H A DX86SchedHaswell.td101 def : WriteRes<SchedRW, ExePorts> {
118 def : WriteRes<WriteRMW, [HWPort237,HWPort4]>;
126 def : WriteRes<WriteZero, []>;
173 def : WriteRes<WriteSETCC, [HWPort06]>; // Setcc.
190 def : WriteRes<WriteLEA, [HWPort15]>;
470 def : WriteRes<WriteVecInsert, [HWPort5]> {
493 def : WriteRes<WritePCmpIStrM, [HWPort0]> {
517 def : WriteRes<WritePCmpIStrI, [HWPort0]> {
547 def : WriteRes<WriteAESDecEnc, [HWPort5]> {
558 def : WriteRes<WriteAESIMC, [HWPort5]> {
[all …]
H A DX86SchedSkylakeClient.td95 def : WriteRes<SchedRW, ExePorts> {
112 def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>;
130 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
162 def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
212 def : WriteRes<WriteZero, []>;
418 def : WriteRes<WriteVecInsert, [SKLPort5]> {
483 def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
507 def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
571 def : WriteRes<WriteCLMul, [SKLPort5]> {
596 def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>;
[all …]
H A DX86ScheduleBtVer2.td126 def : WriteRes<SchedRW, ExePorts> {
146 def : WriteRes<SchedRW, ExePorts> {
166 def : WriteRes<SchedRW, ExePorts> {
229 def : WriteRes<WriteLAHFSAHF, [JALU01]>;
239 def : WriteRes<WriteLEA, [JALU01]>;
273 def : WriteRes<WriteStore, [JSAGU]>;
274 def : WriteRes<WriteStoreNT, [JSAGU]>;
275 def : WriteRes<WriteMove, [JALU01]>;
280 def : WriteRes<WriteSTMXCSR, [JSAGU]>;
290 def : WriteRes<WriteZero, []>;
[all …]
H A DX86SchedBroadwell.td96 def : WriteRes<SchedRW, ExePorts> {
113 def : WriteRes<WriteRMW, [BWPort237,BWPort4]>;
131 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
165 def : WriteRes<WriteSETCC, [BWPort06]>; // Setcc.
215 def : WriteRes<WriteZero, []>;
428 def : WriteRes<WriteVecInsert, [BWPort5]> {
438 def : WriteRes<WriteVecExtract, [BWPort0,BWPort5]> {
492 def : WriteRes<WritePCmpIStrM, [BWPort0]> {
516 def : WriteRes<WritePCmpIStrI, [BWPort0]> {
596 def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
[all …]
H A DX86ScheduleZnver2.td136 def : WriteRes<SchedRW, ExePorts> {
157 def : WriteRes<SchedRW, ExePorts> {
174 def : WriteRes<WriteRMW, [Zn2AGU]>;
176 def : WriteRes<WriteStore, [Zn2AGU]>;
177 def : WriteRes<WriteStoreNT, [Zn2AGU]>;
178 def : WriteRes<WriteMove, [Zn2ALU]>;
185 def : WriteRes<WriteZero, []>;
186 def : WriteRes<WriteLEA, [Zn2ALU]>;
212 def : WriteRes<WriteSETCC, [Zn2ALU]>;
468 def : WriteRes<WriteFence, [Zn2AGU]>;
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM7.td72 def : WriteRes<WriteMUL16, [M7UnitMAC]>;
73 def : WriteRes<WriteMUL32, [M7UnitMAC]>;
88 def : WriteRes<WriteDIV, [M7UnitALU]> {
155 def : WriteRes<WriteVLD1, []>;
156 def : WriteRes<WriteVLD2, []>;
157 def : WriteRes<WriteVLD3, []>;
158 def : WriteRes<WriteVLD4, []>;
159 def : WriteRes<WriteVST1, []>;
160 def : WriteRes<WriteVST2, []>;
161 def : WriteRes<WriteVST3, []>;
[all …]
H A DARMScheduleR52.td74 def : WriteRes<WriteDIV, [R52UnitDiv]> {
79 def : WriteRes<WriteBr, [R52UnitB]> { let Latency = 0; }
108 def : WriteRes<WriteFPDIV32, [R52UnitDiv]> {
113 def : WriteRes<WriteFPDIV64, [R52UnitDiv]> {
122 def : WriteRes<WriteVST1, []>;
123 def : WriteRes<WriteVST2, []>;
124 def : WriteRes<WriteVST3, []>;
125 def : WriteRes<WriteVST4, []>;
719 def : WriteRes<WriteVLD2, [R52UnitLd]> {
725 def : WriteRes<WriteVLD3, [R52UnitLd]> {
[all …]
H A DARMScheduleM4.td37 class M4UnitL1<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 1; }
38 class M4UnitL2<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 2; }
39 class M4UnitL3<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 3; }
40 class M4UnitL14<SchedWrite write> : WriteRes<write, [M4Unit]> { let Latency = 14; }
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td64 def : WriteRes<WriteLD, [LdSt]> { let Latency = 2; }
65 def : WriteRes<WriteST, [LdSt]> { let Latency = 2; }
66 def : WriteRes<WriteLDSW, [LdSt]> { let Latency = 2; }
67 def : WriteRes<WriteSTSW, [LdSt]> { let Latency = 4; }
68 def : WriteRes<WriteALU, [ALU]> { let Latency = 1; }

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