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Searched refs:WriteI (Results 1 – 19 of 19) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveInterval.cpp1195 WriteI = ReadI = LR->begin(); in add()
1205 if (ReadI != WriteI) in add()
1208 if (ReadI == WriteI) in add()
1212 *WriteI++ = *ReadI++; in add()
1242 if (WriteI != LR->begin() && coalescable(WriteI[-1], Seg)) { in add()
1243 WriteI[-1].end = std::max(WriteI[-1].end, Seg.end); in add()
1248 if (WriteI != ReadI) { in add()
1249 *WriteI++ = Seg; in add()
1254 if (WriteI == E) { in add()
1256 WriteI = ReadI = LR->end(); in add()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX.td52 def : WriteRes<WriteI, [THXT8XUnitALU]> { let Latency = 1; }
202 def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
206 def THXT8XReadShifted : SchedReadAdvance<1, [WriteImm, WriteI,
210 def THXT8XReadNotShifted : SchedReadAdvance<2, [WriteImm, WriteI,
226 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
230 def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI,
236 def : ReadAdvance<ReadID, 1, [WriteImm, WriteI,
265 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64SchedA53.td61 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 3; }
159 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
163 def A53ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
167 def A53ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
183 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
187 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
193 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
204 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64SchedA55.td64 def : WriteRes<WriteI, [CortexA55UnitALU]> { let Latency = 3; } // ALU
190 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
195 def CortexA55ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
199 def CortexA55ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
214 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
218 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
224 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
239 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64SchedThunderX2T99.td417 def : WriteRes<WriteI, [THX2T99I012]> {
423 def : InstRW<[WriteI],
436 def : InstRW<[WriteI], (instrs COPY)>;
583 // NOTE: Handled by WriteI.
600 // NOTE: Handled by WriteLD, WriteI.
721 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRBpost)>;
722 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRDpost)>;
723 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRHpost)>;
724 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRQpost)>;
725 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRSpost)>;
[all …]
H A DAArch64SchedKryo.td66 def : WriteRes<WriteI, [KryoUnitXY]> { let Latency = 1; }
130 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64SchedA57.td75 def : SchedAlias<WriteI, A57Write_1cyc_1I>;
131 def : InstRW<[WriteI], (instrs COPY)>;
146 SchedVar<NoSchedPred, [WriteI]>]>;
603 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRBpost)>;
609 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRDpost)>;
616 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRHpost)>;
622 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRQpost)>;
632 def : InstRW<[A57Write_5cyc_1L, WriteI], (instrs LDRSpost)>;
H A DAArch64SchedFalkor.td71 def : WriteRes<WriteI, []> { let Unsupported = 1; }
H A DAArch64Schedule.td24 def WriteI : SchedWrite; // ALU
H A DAArch64SchedA64FX.td812 def : WriteRes<WriteI, [A64FXGI2456]> {
817 def : InstRW<[WriteI],
830 def : InstRW<[WriteI], (instrs COPY)>;
972 // NOTE: Handled by WriteI.
989 // NOTE: Handled by WriteLD, WriteI.
1109 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRBpost)>;
1110 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRDpost)>;
1111 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRHpost)>;
1112 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRQpost)>;
1113 def : InstRW<[A64FXWrite_LDR01, WriteI], (instrs LDRSpost)>;
[all …]
H A DAArch64SchedCyclone.td128 SchedVar<NoSchedPred, [WriteI]>]>;
152 def : WriteRes<WriteI, [CyUnitI]>;
294 def : InstRW<[WriteI], (instrs ISB)>;
361 def CyWriteCopyToGPR : WriteSequence<[WriteLD, WriteI]>;
H A DAArch64SchedThunderX3T110.td676 def : WriteRes<WriteI, [THX3T110I0123]> {
682 def : InstRW<[WriteI],
695 def : InstRW<[WriteI], (instrs COPY)>;
842 // NOTE: Handled by WriteI.
859 // NOTE: Handled by WriteLD, WriteI.
953 def : InstRW<[THX3T110Write_5Cyc_LS01_I0123, WriteI],
967 def : InstRW<[THX3T110Write_4Cyc_LS01_I0123_I0123, WriteI],
H A DAArch64SchedTSV110.td55 def : WriteRes<WriteI, [TSV110UnitALUAB]> { let Latency = 1; }
117 def : InstRW<[WriteI], (instrs COPY)>;
H A DAArch64InstrFormats.td1936 Sched<[WriteI, ReadI]> {
1972 Sched<[WriteI, ReadI]> {
1998 Sched<[WriteI, ReadI, ReadI]> {
2022 Sched<[WriteI, ReadI, ReadI]> {
2278 Sched<[WriteI]> {
2342 Sched<[WriteI, ReadI]> {
2373 Sched<[WriteI, ReadI]> {
2399 Sched<[WriteI, ReadI, ReadI]>;
2815 Sched<[WriteI, ReadI]> {
2911 Sched<[WriteI, ReadI, ReadI]>;
[all …]
H A DAArch64SchedExynosM3.td198 def : SchedAlias<WriteI, M3WriteA1>;
H A DAArch64SchedExynosM5.td544 def : SchedAlias<WriteI, M5WriteA1W>;
H A DAArch64SchedExynosM4.td511 def : SchedAlias<WriteI, M4WriteA1>;
H A DAArch64InstrInfo.td2296 Sched<[WriteI, WriteLD, WriteI, WriteBrReg]>;
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLiveInterval.h931 LiveRange::iterator WriteI; variable