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Searched refs:WR2 (Results 1 – 6 of 6) sorted by relevance

/freebsd-13.1/sys/arm/freescale/imx/
H A Dimx_wdog.c97 WR2(struct imx_wdog_softc *sc, bus_size_t offs, uint16_t val) in WR2() function
117 WR2(sc, WDOG_CR_REG, reg | WDOG_CR_WDE); in imx_wdog_enable()
120 WR2(sc, WDOG_SR_REG, WDOG_SR_STEP1); in imx_wdog_enable()
121 WR2(sc, WDOG_SR_REG, WDOG_SR_STEP2); in imx_wdog_enable()
126 WR2(sc, WDOG_MCR_REG, reg & ~WDOG_MCR_PDE); in imx_wdog_enable()
209 WR2(sc, WDOG_CR_REG, WDOG_CR_WDT | RD2(sc, WDOG_CR_REG)); in imx_wdog_attach()
213 WR2(sc, WDOG_ICR_REG, WDOG_ICR_WIE); /* Enable, count is 0. */ in imx_wdog_attach()
/freebsd-13.1/sys/dev/sdhci/
H A Dsdhci.c355 WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN); in sdhci_set_clock()
378 WR2(slot, BCM577XX_HOST_CONTROL, clk_sel); in sdhci_set_clock()
417 WR2(slot, SDHCI_CLOCK_CONTROL, clk); in sdhci_set_clock()
420 WR2(slot, SDHCI_CLOCK_CONTROL, clk); in sdhci_set_clock()
436 WR2(slot, SDHCI_CLOCK_CONTROL, clk); in sdhci_set_clock()
1238 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1305 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1320 WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);
1623 WR2(slot, SDHCI_TRANSFER_MODE, mode);
1890 WR2(slot, SDHCI_BLOCK_SIZE, blksz);
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/freebsd-13.1/sys/dev/ffec/
H A Dif_ffec.c219 WR2(struct ffec_softc *sc, bus_size_t off, uint16_t val) in WR2() function
295 WR2(sc, FEC_MIIGSK_ENR, 0); in ffec_miigasket_setup()
299 WR2(sc, FEC_MIIGSK_CFGR, ifmode); in ffec_miigasket_setup()
301 WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN); in ffec_miigasket_setup()
/freebsd-13.1/sys/arm/broadcom/bcm2835/
H A Dbcm2835_sdhost.c274 WR2(struct bcm_sdhost_softc *sc, bus_size_t off, uint16_t val) in WR2() function
1098 WR2(sc, HC_BLOCKSIZE, val); in bcm_sdhost_write_2()
1105 WR2(sc, HC_BLOCKCOUNT, val); in bcm_sdhost_write_2()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/
H A DHexagonDisassembler.cpp614 Hexagon::WR2, Hexagon::W3, Hexagon::WR3, Hexagon::W4, Hexagon::WR4, in DecodeHvxWRRegisterClass()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonRegisterInfo.td229 def WR2 : Rd< 5, "v4:5", [V4, V5, VFR2]>, DwarfRegNum<[163]>;