| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 175 if (ValueVT.isVector()) in getCopyFromParts()
184 if (ValueVT.isInteger()) { in getCopyFromParts()
257 if (PartEVT == ValueVT) in getCopyFromParts()
398 if (PartEVT == ValueVT) in getCopyFromPartsVector()
430 TLI.isTypeLegal(ValueVT)) in getCopyFromPartsVector()
486 if (ValueVT.isVector()) in getCopyToParts()
500 if (PartEVT == ValueVT) { in getCopyToParts()
515 ValueVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); in getCopyToParts()
547 if (PartEVT != ValueVT) { in getCopyToParts()
658 if (PartEVT == ValueVT) { in getCopyToPartsVector()
[all …]
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| H A D | LegalizeTypesGeneric.cpp | 256 EVT ValueVT = LD->getValueType(0); in ExpandRes_NormalLoad() local
257 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandRes_NormalLoad()
281 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandRes_NormalLoad()
466 EVT ValueVT = St->getValue().getValueType(); in ExpandOp_NormalStore() local
467 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), ValueVT); in ExpandOp_NormalStore()
478 if (TLI.hasBigEndianPartOrdering(ValueVT, DAG.getDataLayout())) in ExpandOp_NormalStore()
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| H A D | FunctionLoweringInfo.cpp | 394 EVT ValueVT = ValueVTs[Value]; in CreateRegs() local
395 MVT RegisterVT = TLI->getRegisterType(Ty->getContext(), ValueVT); in CreateRegs()
397 unsigned NumRegs = TLI->getNumRegisters(Ty->getContext(), ValueVT); in CreateRegs()
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| H A D | LegalizeVectorTypes.cpp | 4926 EVT ValueVT = StVal.getValueType(); in WidenVecOp_MSTORE() local
4928 ValueVT.getVectorElementType(), in WidenVecOp_MSTORE()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFrameLowering.cpp | 82 for (EVT ValueVT : ValueVTs) in getLocalForStackObject() local
83 FuncInfo->addLocal(ValueVT.getSimpleVT()); in getLocalForStackObject()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 148 EVT ValueVT = LD->getValueType(0); in SelectIndexedLoad() local
149 if (ValueVT == MVT::i64 && ExtType != ISD::NON_EXTLOAD) { in SelectIndexedLoad()
153 ValueVT = MVT::i32; in SelectIndexedLoad()
157 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, in SelectIndexedLoad()
169 MachineSDNode *L = CurDAG->getMachineNode(Opcode, dl, ValueVT, MVT::Other, in SelectIndexedLoad()
471 EVT ValueVT = Value.getValueType(); in SelectIndexedStore() local
518 if (ST->isTruncatingStore() && ValueVT.getSizeInBits() == 64) { in SelectIndexedStore()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 5727 MVT ValueVT = Node->getSimpleValueType(0); in Select() local
5733 if (!ValueVT.isVector() || !MaskVT.isVector()) in Select()
5736 unsigned NumElts = ValueVT.getVectorNumElements(); in Select()
5737 MVT ValueSVT = ValueVT.getVectorElementType(); in Select()
5770 assert(EVT(MaskVT) == EVT(ValueVT).changeVectorElementTypeToInteger() && in Select()
5801 SDVTList VTs = CurDAG->getVTList(ValueVT, MaskVT, MVT::Other); in Select()
5824 MVT ValueVT = Value.getSimpleValueType(); in Select() local
5829 if (!ValueVT.isVector()) in Select()
5832 unsigned NumElts = ValueVT.getVectorNumElements(); in Select()
5833 MVT ValueSVT = ValueVT.getVectorElementType(); in Select()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.h | 487 MVT PartVT, EVT ValueVT,
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| H A D | RISCVISelLowering.cpp | 8982 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
8983 if (IsABIRegCopy && ValueVT == MVT::f16 && PartVT == MVT::f32) { in splitValueIntoRegisterParts()
8995 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in splitValueIntoRegisterParts()
8997 EVT ValueEltVT = ValueVT.getVectorElementType(); in splitValueIntoRegisterParts()
8999 unsigned ValueVTBitSize = ValueVT.getSizeInBits().getKnownMinSize(); in splitValueIntoRegisterParts()
9022 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
9024 if (IsABIRegCopy && ValueVT == MVT::f16 && PartVT == MVT::f32) { in joinRegisterPartsIntoValue()
9034 if (ValueVT.isScalableVector() && PartVT.isScalableVector()) { in joinRegisterPartsIntoValue()
9037 EVT ValueEltVT = ValueVT.getVectorElementType(); in joinRegisterPartsIntoValue()
9042 EVT SameEltTypeVT = ValueVT; in joinRegisterPartsIntoValue()
[all …]
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.h | 548 MVT PartVT, EVT ValueVT,
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| H A D | SystemZISelLowering.cpp | 1394 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
1395 assert((ValueVT != MVT::i128 || in splitValueIntoRegisterParts()
1399 if (ValueVT == MVT::i128 && NumParts == 1) { in splitValueIntoRegisterParts()
1409 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
1410 assert((ValueVT != MVT::i128 || in joinRegisterPartsIntoValue()
1414 if (ValueVT == MVT::i128 && NumParts == 1) in joinRegisterPartsIntoValue()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.h | 888 MVT PartVT, EVT ValueVT,
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| H A D | ARMISelLowering.cpp | 4333 EVT ValueVT = Val.getValueType(); in splitValueIntoRegisterParts() local
4334 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) && in splitValueIntoRegisterParts()
4336 unsigned ValueBits = ValueVT.getSizeInBits(); in splitValueIntoRegisterParts()
4349 MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const { in joinRegisterPartsIntoValue() argument
4351 if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) && in joinRegisterPartsIntoValue()
4353 unsigned ValueBits = ValueVT.getSizeInBits(); in joinRegisterPartsIntoValue()
4359 Val = DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); in joinRegisterPartsIntoValue()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 3708 MVT PartVT, EVT ValueVT, in joinRegisterPartsIntoValue() argument
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