| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SelectionDAGInfo.cpp | 111 unsigned ValReg; in EmitTargetCodeForMemset() local
118 ValReg = X86::EAX; in EmitTargetCodeForMemset()
123 ValReg = X86::RAX; in EmitTargetCodeForMemset()
129 ValReg = X86::AX; in EmitTargetCodeForMemset()
134 ValReg = X86::AL; in EmitTargetCodeForMemset()
144 Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT), in EmitTargetCodeForMemset()
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| H A D | X86FastISel.cpp | 92 bool X86FastEmitStore(EVT VT, unsigned ValReg, X86AddressMode &AM,
487 bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, X86AddressMode &AM, in X86FastEmitStore() argument
507 .addReg(ValReg).addImm(1); in X86FastEmitStore()
508 ValReg = AndResult; in X86FastEmitStore()
650 ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); in X86FastEmitStore()
653 addFullAddress(MIB, AM).addReg(ValReg); in X86FastEmitStore()
697 Register ValReg = getRegForValue(Val); in X86FastEmitStore() local
698 if (ValReg == 0) in X86FastEmitStore()
701 return X86FastEmitStore(VT, ValReg, AM, MMO, Aligned); in X86FastEmitStore()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 1062 Register CallLowering::ValueHandler::extendRegister(Register ValReg, in extendRegister() argument
1069 return ValReg; in extendRegister()
1073 return ValReg; in extendRegister()
1077 const LLT ValRegTy = MRI.getType(ValReg); in extendRegister()
1082 ValReg = MIRBuilder.buildPtrToInt(IntPtrTy, ValReg).getReg(0); in extendRegister()
1091 return ValReg; in extendRegister()
1093 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg); in extendRegister()
1098 MIRBuilder.buildSExt(NewReg, ValReg); in extendRegister()
1103 MIRBuilder.buildZExt(NewReg, ValReg); in extendRegister()
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| H A D | LegalizerHelper.cpp | 4073 Register ValReg = LdStMI.getReg(0); in reduceLoadStoreWidth() local
4075 LLT ValTy = MRI.getType(ValReg); in reduceLoadStoreWidth()
4090 if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs, in reduceLoadStoreWidth()
4143 insertParts(ValReg, ValTy, NarrowTy, NarrowRegs, in reduceLoadStoreWidth()
7171 Register ValReg = MI.getOperand(ValRegIndex).getReg(); in lowerReadWriteRegister() local
7172 const LLT Ty = MRI.getType(ValReg); in lowerReadWriteRegister()
7181 MIRBuilder.buildCopy(ValReg, PhysReg); in lowerReadWriteRegister()
7183 MIRBuilder.buildCopy(PhysReg, ValReg); in lowerReadWriteRegister()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVExpandAtomicPseudoInsts.cpp | 380 MachineBasicBlock *MBB, Register ValReg, in insertSext() argument
382 BuildMI(MBB, DL, TII->get(RISCV::SLL), ValReg) in insertSext()
383 .addReg(ValReg) in insertSext()
385 BuildMI(MBB, DL, TII->get(RISCV::SRA), ValReg) in insertSext()
386 .addReg(ValReg) in insertSext()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCOptAddrMode.cpp | 426 Register ValReg = IsLoad ? Ldst->getOperand(0).getReg() : Register(); in canSinkLoadStoreTo() local
435 if (ValReg && MI->readsVirtualRegister(ValReg)) in canSinkLoadStoreTo()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMAsmPrinter.cpp | 1898 Register ValReg = MI->getOperand(1).getReg(); in emitInstruction() local
1902 .addReg(ValReg) in emitInstruction()
1909 .addReg(ValReg) in emitInstruction()
1912 .addReg(ValReg) in emitInstruction()
1919 .addReg(ValReg) in emitInstruction()
1964 Register ValReg = MI->getOperand(1).getReg(); in emitInstruction() local
1968 .addReg(ValReg) in emitInstruction()
1978 .addReg(ValReg) in emitInstruction()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 990 Register ValReg = MI.getOperand(0).getReg(); in legalizeLoadStore() local
991 const LLT ValTy = MRI.getType(ValReg); in legalizeLoadStore()
1005 auto Bitcast = MIRBuilder.buildBitcast(NewTy, ValReg); in legalizeLoadStore()
1009 MIRBuilder.buildBitcast(ValReg, NewLoad); in legalizeLoadStore()
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| H A D | AArch64InstructionSelector.cpp | 2749 const Register ValReg = I.getOperand(0).getReg(); in select() local
2750 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI); in select()
2772 IsStore ? NewInst.addUse(ValReg) : NewInst.addDef(ValReg); in select()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CallLowering.h | 302 Register extendRegister(Register ValReg, CCValAssign &VA,
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstructionSelector.cpp | 1306 Register ValReg = MI.getOperand(3).getReg(); in selectDSOrderedIntrinsic() local
1309 .addReg(ValReg) in selectDSOrderedIntrinsic()
2733 Register ValReg = MI.getOperand(2).getReg(); in selectG_INSERT_VECTOR_ELT() local
2737 LLT ValTy = MRI->getType(ValReg); in selectG_INSERT_VECTOR_ELT()
2742 const RegisterBank *ValRB = RBI.getRegBank(ValReg, *MRI, TRI); in selectG_INSERT_VECTOR_ELT()
2759 !RBI.constrainGenericRegister(ValReg, *ValRC, *MRI) || in selectG_INSERT_VECTOR_ELT()
2784 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
2794 .addReg(ValReg) in selectG_INSERT_VECTOR_ELT()
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| H A D | AMDGPULegalizerInfo.cpp | 2488 Register ValReg = MI.getOperand(0).getReg(); in legalizeLoad() local
2489 LLT ValTy = MRI.getType(ValReg); in legalizeLoad()
2524 B.buildTrunc(ValReg, WideLoad).getReg(0); in legalizeLoad()
2532 B.buildExtract(ValReg, WideLoad, 0); in legalizeLoad()
2537 WideLoad = Helper.widenWithUnmerge(WideTy, ValReg); in legalizeLoad()
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