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Searched refs:VTSize (Results 1 – 10 of 10) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSelectionDAGInfo.cpp200 unsigned VTSize = 4; in EmitTargetCodeForMemcpy() local
238 DstPtrInfo = DstPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
239 SrcPtrInfo = SrcPtrInfo.getWithOffset(NumRegs * VTSize); in EmitTargetCodeForMemcpy()
259 VTSize = getRemainingSize(BytesLeft); in EmitTargetCodeForMemcpy()
266 SrcOff += VTSize; in EmitTargetCodeForMemcpy()
267 BytesLeft -= VTSize; in EmitTargetCodeForMemcpy()
276 VTSize = getRemainingSize(BytesLeft); in EmitTargetCodeForMemcpy()
282 DstOff += VTSize; in EmitTargetCodeForMemcpy()
283 BytesLeft -= VTSize; in EmitTargetCodeForMemcpy()
H A DARMCallLowering.cpp75 unsigned VTSize = VT.getSimpleVT().getSizeInBits(); in isSupportedType() local
77 if (VTSize == 64) in isSupportedType()
81 return VTSize == 1 || VTSize == 8 || VTSize == 16 || VTSize == 32; in isSupportedType()
H A DARMISelLowering.cpp7986 uint64_t VTSize = VT.getFixedSizeInBits(); in ReconstructShuffle() local
7987 if (SrcVTSize == VTSize) in ReconstructShuffle()
7993 unsigned NumSrcElts = VTSize / EltVT.getFixedSizeInBits(); in ReconstructShuffle()
7996 if (SrcVTSize < VTSize) { in ReconstructShuffle()
7997 if (2 * SrcVTSize != VTSize) in ReconstructShuffle()
8007 if (SrcVTSize != 2 * VTSize) in ReconstructShuffle()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp921 unsigned VTSize = VT.getScalarSizeInBits(); in earlyExpandDIVFIX() local
949 assert(SatW <= VTSize && in earlyExpandDIVFIX()
3441 unsigned VTSize = VT.getScalarSizeInBits(); in ExpandIntRes_MULFIX() local
3462 APInt MinVal = APInt::getSignedMinValue(VTSize); in ExpandIntRes_MULFIX()
3463 APInt MaxVal = APInt::getSignedMaxValue(VTSize); in ExpandIntRes_MULFIX()
3476 APInt MaxVal = APInt::getMaxValue(VTSize); in ExpandIntRes_MULFIX()
3544 if (Scale == VTSize) in ExpandIntRes_MULFIX()
3577 } else if (Scale < VTSize) { in ExpandIntRes_MULFIX()
3597 unsigned OverflowBits = VTSize - Scale + 1; in ExpandIntRes_MULFIX()
3629 } else if (Scale < VTSize) { in ExpandIntRes_MULFIX()
[all …]
H A DTargetLowering.cpp226 unsigned VTSize = VT.getSizeInBits() / 8; in findOptimalMemOpLowering() local
227 while (VTSize > Size) { in findOptimalMemOpLowering()
264 VTSize = Size; in findOptimalMemOpLowering()
267 VTSize = NewVTSize; in findOptimalMemOpLowering()
275 Size -= VTSize; in findOptimalMemOpLowering()
8140 unsigned VTSize = VT.getScalarSizeInBits(); in expandFixedPointMul() local
8170 APInt MaxVal = APInt::getMaxValue(VTSize); in expandFixedPointMul()
8176 assert(((Signed && Scale < VTSize) || (!Signed && Scale <= VTSize)) && in expandFixedPointMul()
8199 if (Scale == VTSize) in expandFixedPointMul()
8220 APInt MaxVal = APInt::getMaxValue(VTSize); in expandFixedPointMul()
[all …]
H A DSelectionDAG.cpp6472 if (VTSize > Size) { in getMemcpyLoadsAndStores()
6476 SrcOff -= VTSize - Size; in getMemcpyLoadsAndStores()
6477 DstOff -= VTSize - Size; in getMemcpyLoadsAndStores()
6535 SrcOff += VTSize; in getMemcpyLoadsAndStores()
6536 DstOff += VTSize; in getMemcpyLoadsAndStores()
6537 Size -= VTSize; in getMemcpyLoadsAndStores()
6663 SrcOff += VTSize; in getMemmoveLoadsAndStores()
6677 DstOff += VTSize; in getMemmoveLoadsAndStores()
6759 if (VTSize > Size) { in getMemsetStores()
6763 DstOff -= VTSize - Size; in getMemsetStores()
[all …]
H A DDAGCombiner.cpp16783 TypeSize VTSize = VT.getSizeInBits(); in TransformFPLoadStorePair() local
16787 if (VTSize.isScalable()) in TransformFPLoadStorePair()
16790 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VTSize.getFixedSize()); in TransformFPLoadStorePair()
19223 uint64_t VTSize = VT.getFixedSizeInBits(); in createBuildVecShuffle() local
19233 if ((VTSize % InVT1Size == 0) && InVT1 == InVT2) { in createBuildVecShuffle()
19236 unsigned NumConcats = VTSize / InVT1Size; in createBuildVecShuffle()
19243 } else if (InVT1Size == VTSize * 2) { in createBuildVecShuffle()
19279 } else if (InVT2Size * 2 == VTSize && InVT1Size == VTSize) { in createBuildVecShuffle()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp3329 if (VTSize < InVTSize) { in LowerVectorFP_TO_INT()
3337 if (VTSize > InVTSize) { in LowerVectorFP_TO_INT()
3444 if (VTSize < InVTSize) { in LowerVectorINT_TO_FP()
3452 if (VTSize > InVTSize) { in LowerVectorINT_TO_FP()
8249 if (VTSize == 16) in getRegForInlineAsmConstraint()
8251 if (VTSize == 32) in getRegForInlineAsmConstraint()
8253 if (VTSize == 64) in getRegForInlineAsmConstraint()
8255 if (VTSize == 128) in getRegForInlineAsmConstraint()
8611 if (SrcVTSize == VTSize) in ReconstructShuffle()
8620 if (SrcVTSize < VTSize) { in ReconstructShuffle()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp3457 uint64_t VTSize = DL.getTypeStoreSizeInBits(FixedVectorType::get(EltTy, N)); in canMapToVector() local
3458 if (VTSize < MinVecRegSize || VTSize > MaxVecRegSize || VTSize != DL.getTypeStoreSizeInBits(T)) in canMapToVector()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp19907 unsigned VTSize = VT.getSizeInBits(); in lowerFPToIntToFP() local
19910 MVT VecVT = MVT::getVectorVT(VT, 128 / VTSize); in lowerFPToIntToFP()
19916 IntSize != VTSize ? X86ISD::CVTSI2P : (unsigned)ISD::SINT_TO_FP; in lowerFPToIntToFP()