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Searched refs:VT1 (Results 1 – 23 of 23) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/
H A DLegacyPassNameParser.h89 static int ValCompare(const PassNameParser::OptionInfo *VT1, in ValCompare() argument
91 return VT1->Name.compare(VT2->Name); in ValCompare()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURewriteOutArguments.cpp193 auto *VT1 = dyn_cast<FixedVectorType>(Ty1); in isVec3ToVec4Shuffle() local
194 if (!VT0 || !VT1) in isVec3ToVec4Shuffle()
198 VT1->getNumElements() != 4) in isVec3ToVec4Shuffle()
202 DL->getTypeSizeInBits(VT1->getElementType()); in isVec3ToVec4Shuffle()
H A DAMDGPUISelLowering.h167 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.h137 bool isTruncateFree(EVT VT1, EVT VT2) const override;
141 bool isZExtFree(EVT VT1, EVT VT2) const override;
H A DBPFISelLowering.cpp199 bool BPFTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree() argument
200 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
202 unsigned NumBits1 = VT1.getSizeInBits(); in isTruncateFree()
215 bool BPFTargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree() argument
216 if (!getHasAlu32() || !VT1.isInteger() || !VT2.isInteger()) in isZExtFree()
218 unsigned NumBits1 = VT1.getSizeInBits(); in isZExtFree()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h117 bool isTruncateFree(EVT VT1, EVT VT2) const override;
128 bool isZExtFree(EVT VT1, EVT VT2) const override;
H A DMSP430ISelLowering.cpp1396 bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree() argument
1397 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
1400 return (VT1.getFixedSizeInBits() > VT2.getFixedSizeInBits()); in isTruncateFree()
1408 bool MSP430TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree() argument
1410 return 0 && VT1 == MVT::i8 && VT2 == MVT::i16; in isZExtFree()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h603 SDVTList getVTList(EVT VT1, EVT VT2);
604 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3);
605 SDVTList getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4);
1412 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2);
1413 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
1415 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
1417 SDNode *SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1,
1447 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1449 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
1451 MachineSDNode *getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT1,
[all …]
H A DTargetLowering.h1472 EVT VT1; in getRegisterType() local
1475 (void)getVectorTypeBreakdown(Context, VT, VT1, in getRegisterType()
1505 EVT VT1; variable
1508 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp8154 ID.AddInteger(VT1.getRawBits()); in getVTList()
8161 Array[0] = VT1; in getVTList()
8172 ID.AddInteger(VT1.getRawBits()); in getVTList()
8180 Array[0] = VT1; in getVTList()
8192 ID.AddInteger(VT1.getRawBits()); in getVTList()
8201 Array[0] = VT1; in getVTList()
8414 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
8420 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
8434 SDVTList VTs = getVTList(VT1, VT2); in SelectNodeTo()
8622 SDVTList VTs = getVTList(VT1, VT2); in getMachineNode()
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H A DLegalizeVectorTypes.cpp4318 EVT VT1 = getSetCCResultType(getSETCCOperandType(SETCC1)); in WidenVSELECTMask() local
4320 unsigned ScalarBits1 = VT1.getScalarSizeInBits(); in WidenVSELECTMask()
4327 EVT NarrowVT = ((ScalarBits0 < ScalarBits1) ? VT0 : VT1); in WidenVSELECTMask()
4328 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0); in WidenVSELECTMask()
4341 SETCC1 = convertMask(SETCC1, VT1, MaskVT); in WidenVSELECTMask()
H A DDAGCombiner.cpp9117 EVT VT1 = Op0.getOperand(0).getValueType(); in combineABSToABD() local
9121 if (VT1 != VT2 || !TLI.isOperationLegalOrCustom(ABDOpcode, VT1)) in combineABSToABD()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1203 bool isTruncateFree(EVT VT1, EVT VT2) const override;
1216 bool isZExtFree(EVT VT1, EVT VT2) const override;
1236 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
H A DX86ISelLowering.cpp32013 unsigned NumBits1 = VT1.getSizeInBits(); in isTruncateFree()
32029 EVT VT1 = Val.getValueType(); in isZExtFree() local
32030 if (isZExtFree(VT1, VT2)) in isZExtFree()
32036 if (!VT1.isSimple() || !VT1.isInteger() || in isZExtFree()
32040 switch (VT1.getSimpleVT().SimpleTy) { in isZExtFree()
32121 return !(VT1 == MVT::i32 && VT2 == MVT::i16); in isNarrowingProfitable()
35784 MVT VT1 = V1.getSimpleValueType(); in combineX86ShuffleChain() local
35786 assert(VT1.getSizeInBits() == RootSizeInBits && in combineX86ShuffleChain()
35826 if (VT1 == VT2 && VT1.getSizeInBits() == RootSizeInBits && VT1.isVector()) { in combineX86ShuffleChain()
35828 unsigned NumElts = VT1.getVectorNumElements(); in combineX86ShuffleChain()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h573 bool isTruncateFree(EVT VT1, EVT VT2) const override;
578 bool isZExtFree(EVT VT1, EVT VT2) const override;
H A DAArch64ISelLowering.cpp11339 bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree() argument
11340 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
11342 uint64_t NumBits1 = VT1.getFixedSizeInBits(); in isTruncateFree()
11384 bool AArch64TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { in isZExtFree() argument
11385 if (VT1.isVector() || VT2.isVector() || !VT1.isInteger() || !VT2.isInteger()) in isZExtFree()
11387 unsigned NumBits1 = VT1.getSizeInBits(); in isZExtFree()
11393 EVT VT1 = Val.getValueType(); in isZExtFree() local
11394 if (isZExtFree(VT1, VT2)) { in isZExtFree()
11402 return (VT1.isSimple() && !VT1.isVector() && VT1.isInteger() && in isZExtFree()
11404 VT1.getSizeInBits() <= 32); in isZExtFree()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp183 EVT VT1 = Val.getValueType(); in isZExtFree() local
184 if (!VT1.isSimple() || !VT1.isInteger() || in isZExtFree()
188 switch (VT1.getSimpleVT().SimpleTy) { in isZExtFree()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h133 bool isTruncateFree(EVT VT1, EVT VT2) const override;
H A DHexagonISelLowering.cpp2116 bool HexagonTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree() argument
2117 if (!VT1.isSimple() || !VT2.isSimple()) in isTruncateFree()
2119 return VT1.getSimpleVT() == MVT::i64 && VT2.getSimpleVT() == MVT::i32; in isTruncateFree()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp76 for (MVT VT1 : MVT::fixedlen_vector_valuetypes()) { in MipsSETargetLowering() local
77 setTruncStoreAction(VT0, VT1, Expand); in MipsSETargetLowering()
78 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
79 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
80 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h984 bool isTruncateFree(EVT VT1, EVT VT2) const override;
H A DPPCISelLowering.cpp16205 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { in isTruncateFree() argument
16206 if (!VT1.isInteger() || !VT2.isInteger()) in isTruncateFree()
16208 unsigned NumBits1 = VT1.getSizeInBits(); in isTruncateFree()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp17977 EVT VT1 = Val.getValueType(); in isZExtFree() local
17978 if (!VT1.isSimple() || !VT1.isInteger() || in isZExtFree()
17982 switch (VT1.getSimpleVT().SimpleTy) { in isZExtFree()