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Searched refs:VSELECT (Results 1 – 25 of 25) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp106 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
167 setTargetDAGCombine(ISD::VSELECT); in MipsSETargetLowering()
352 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAIntType()
397 setOperationAction(ISD::VSELECT, Ty, Legal); in addMSAFloatType()
1046 case ISD::VSELECT: in PerformDAGCombine()
1618 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1633 return DAG.getNode(ISD::VSELECT, DL, VecTy, in lowerINTRINSIC_WO_CHAIN()
1641 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1648 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
1679 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h688 VSELECT, enumerator
H A DSelectionDAG.h1081 auto Opcode = Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT;
H A DBasicTTIImpl.h1066 ISD = ISD::VSELECT;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp184 setOperationAction(ISD::VSELECT, T, Custom); in initializeHVXLowering()
270 setTargetDAGCombine(ISD::VSELECT); in initializeHVXLowering()
1719 SDValue VSel = DAG.getNode(ISD::VSELECT, dl, ValTy, Mask, Load, Thru); in LowerHvxMaskedOp()
2088 case ISD::VSELECT: in LowerHvxOperation()
2245 case ISD::VSELECT: { in PerformHvxDAGCombine()
2251 return DAG.getNode(ISD::VSELECT, dl, ty(Op), C0, Ops[2], Ops[1]); in PerformHvxDAGCombine()
H A DHexagonISelLowering.cpp1752 setOperationAction(ISD::VSELECT, MVT::v4i8, Custom); in HexagonTargetLowering()
1753 setOperationAction(ISD::VSELECT, MVT::v2i16, Custom); in HexagonTargetLowering()
1806 setTargetDAGCombine(ISD::VSELECT); in HexagonTargetLowering()
3207 case ISD::VSELECT: return LowerVSELECT(Op, DAG); in LowerOperation()
3293 } else if (Opc == ISD::VSELECT) { in PerformDAGCombine()
3301 SDValue VSel = DCI.DAG.getNode(ISD::VSELECT, dl, ty(Op), C0, in PerformDAGCombine()
/freebsd-13.1/sys/contrib/device-tree/src/arm/
H A Dimx6ul-14x14-evk.dtsi553 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
H A Dimx7-mba7.dtsi422 /* VSELECT */
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorTypes.cpp61 case ISD::VSELECT: R = ScalarizeVecRes_VSELECT(N); break; in ScalarizeVectorResult()
629 case ISD::VSELECT: in ScalarizeVectorOperand()
916 case ISD::VSELECT: in SplitVectorResult()
2181 case ISD::VSELECT: in SplitVectorOperand()
2284 DAG.getNode(ISD::VSELECT, DL, LoOpVT, LoMask, LoOp0, LoOp1); in SplitVecOp_VSELECT()
2286 DAG.getNode(ISD::VSELECT, DL, HiOpVT, HiMask, HiOp0, HiOp1); in SplitVecOp_VSELECT()
2996 case ISD::VSELECT: in WidenVectorResult()
4249 if (N->getOpcode() != ISD::VSELECT) in WidenVSELECTMask()
4548 case ISD::VSELECT: Res = WidenVecOp_VSELECT(N); break; in WidenVectorOperand()
H A DLegalizeVectorOps.cpp398 case ISD::VSELECT: in LegalizeOp()
755 case ISD::VSELECT: in Expand()
H A DSelectionDAGDumper.cpp284 case ISD::VSELECT: return "vselect"; in getOperationName()
H A DTargetLowering.cpp2687 case ISD::VSELECT: { in SimplifyDemandedVectorElts()
5682 if (isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) { in prepareUREMEqFold()
5687 return DAG.getNode(ISD::VSELECT, DL, SETCCVT, TautologicalInvertedChannels, in prepareUREMEqFold()
5944 !isOperationLegalOrCustom(ISD::VSELECT, SETCCVT)) in prepareSREMEqFold()
5970 SDValue Blended = DAG.getNode(ISD::VSELECT, DL, SETCCVT, DivisorIsIntMin, in prepareSREMEqFold()
7993 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandIntMINMAX()
8044 if (VT.isVector() && !isOperationLegalOrCustom(ISD::VSELECT, VT)) in expandAddSubSat()
H A DLegalizeIntegerTypes.cpp78 case ISD::VSELECT: Res = PromoteIntRes_VSELECT(N); break; in PromoteIntegerResult()
1052 return DAG.getNode(ISD::VSELECT, SDLoc(N), in PromoteIntRes_VSELECT()
1503 case ISD::VSELECT: in PromoteIntegerOperand()
1762 if (N->getOpcode() == ISD::VSELECT) in PromoteIntOp_SELECT()
H A DSelectionDAG.cpp3052 case ISD::VSELECT: in computeKnownBits()
3847 case ISD::VSELECT: in ComputeNumSignBits()
6096 case ISD::VSELECT: in getNode()
10044 case ISD::VSELECT: in UnrollVectorOp()
H A DDAGCombiner.cpp1667 case ISD::VSELECT: return visitVSELECT(N); in visit()
9448 assert((N->getOpcode() == ISD::SELECT || N->getOpcode() == ISD::VSELECT) && in foldBoolSelectToLogic()
10359 if (!(N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) || in tryToFoldExtendSelectLoad()
10750 if (LegalOperations || !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT)) in matchVSelectOpSizesWithSetCC()
10754 if (VSel.getOpcode() != ISD::VSELECT || !VSel.hasOneUse() || in matchVSelectOpSizesWithSetCC()
10777 return DAG.getNode(ISD::VSELECT, DL, VT, SetCC, CastA, CastB); in matchVSelectOpSizesWithSetCC()
22982 Test.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT, DL, VT, in buildSqrtEstimateImpl()
H A DSelectionDAGBuilder.cpp3257 Cond.getValueType().isVector() ? ISD::VSELECT : ISD::SELECT; in visitSelect()
3281 !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT); in visitSelect()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp468 setOperationAction(ISD::VSELECT, VT, Expand); in RISCVTargetLowering()
755 setOperationAction(ISD::VSELECT, VT, Custom); in RISCVTargetLowering()
819 setOperationAction(ISD::VSELECT, VT, Custom); in RISCVTargetLowering()
1752 Vec = DAG.getNode(ISD::VSELECT, DL, VT, in lowerBUILD_VECTOR()
1956 return DAG.getNode(ISD::VSELECT, DL, VT, SelectMask, V1, V2); in lowerVECTOR_SHUFFLE()
2620 case ISD::VSELECT: in LowerOperation()
2900 return DAG.getNode(ISD::VSELECT, DL, VT, CondSplat, TrueV, FalseV); in lowerSELECT()
3240 return DAG.getNode(ISD::VSELECT, DL, VecVT, Src, SplatTrueVal, SplatZero); in lowerVectorMaskExt()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp188 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
441 setOperationAction(ISD::VSELECT, VT, Expand); in addMVEVectorTypes()
1528 setTargetDAGCombine(ISD::VSELECT); in ARMTargetLowering()
9919 Combo = DAG.getNode(ISD::VSELECT, dl, VT, Mask, NewLoad, PassThru); in LowerMLOAD()
12874 } else if (N->getOpcode() == ISD::VSELECT) { in PerformVQDMULHCombine()
13007 return DCI.DAG.getNode(ISD::VSELECT, SDLoc(N), Type, Cond, RHS, LHS); in PerformVSELECTCombine()
16019 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
16071 if (ResVT != RetTy || N0->getOpcode() != ISD::VSELECT || in PerformVECREDUCE_ADDCombine()
16199 if (Op->getOpcode() == ISD::VSELECT) in PerformVECREDUCE_ADDCombine()
16208 Ext = DAG.getNode(ISD::VSELECT, dl, N0->getValueType(0), in PerformVECREDUCE_ADDCombine()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp1432 setOperationAction(ISD::VSELECT, MVT::v32i8, Legal); in X86TargetLowering()
2016 setTargetDAGCombine(ISD::VSELECT); in X86TargetLowering()
25088 unsigned OpcodeSelect = ISD::VSELECT; in getVectorMaskingNode()
41038 if (Vec.getOpcode() == ISD::VSELECT && in scalarizeExtEltFP()
41406 if (N->getOpcode() != ISD::VSELECT) in combineVSelectWithAllOnesOrZeros()
41602 if ((N->getOpcode() != ISD::VSELECT && in combineVSelectToBLENDV()
41625 if (!TLI.isOperationLegalOrCustom(ISD::VSELECT, VT)) in combineVSelectToBLENDV()
41645 if ((UI->getOpcode() != ISD::VSELECT && in combineVSelectToBLENDV()
50534 if (Sel.getOpcode() != ISD::VSELECT || in narrowExtractedVectorSelect()
50735 if (InOpcode == ISD::VSELECT && in combineExtractSubvector()
[all …]
H A DX86ISelDAGToDAG.cpp722 (N->getOpcode() == ISD::VSELECT || N->getOpcode() == X86ISD::SELECTS) && in isProfitableToFormMaskedOp()
966 case ISD::VSELECT: { in PreprocessISelDAG()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp915 setTargetDAGCombine(ISD::VSELECT); in AArch64TargetLowering()
1440 setOperationAction(ISD::VSELECT, VT, Expand); in addTypeForNEON()
1595 setOperationAction(ISD::VSELECT, VT, Custom); in addTypeForFixedLengthSVE()
4964 case ISD::VSELECT: in LowerOperation()
7518 return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal); in LowerSELECT()
7529 return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal); in LowerSELECT()
14529 return DAG.getNode(ISD::VSELECT, SDLoc(N), N->getValueType(0), in performIntrinsicCombine()
15950 return DAG.getNode(ISD::VSELECT, SDLoc(N), ResVT, SetCC, in performVSelectCombine()
16642 case ISD::VSELECT: in PerformDAGCombine()
18410 auto ScalableRes = DAG.getNode(ISD::VSELECT, DL, ContainerVT, in LowerFixedLengthVectorSelectToSVE()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp487 setOperationAction(ISD::VSELECT, VT, Expand); in AMDGPUTargetLowering()
526 setOperationAction(ISD::VSELECT, VT, Expand); in AMDGPUTargetLowering()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td586 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp786 setOperationAction(ISD::VSELECT, VT, Legal); in PPCTargetLowering()
1348 setTargetDAGCombine(ISD::VSELECT); in PPCTargetLowering()
15469 case ISD::VSELECT: in PerformDAGCombine()
17077 assert((N->getOpcode() == ISD::VSELECT) && "Need VSELECT node here"); in combineVSelect()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp345 setOperationAction(ISD::VSELECT, VT, Legal); in SystemZTargetLowering()