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Searched refs:VSCALE (Results 1 – 11 of 11) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1202 VSCALE, enumerator
H A DSelectionDAG.h959 return getNode(ISD::VSCALE, DL, VT,
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp174 case ISD::VSCALE: return "vscale"; in getOperationName()
H A DDAGCombiner.cpp2506 if (N0.getOpcode() == ISD::VSCALE && N1.getOpcode() == ISD::VSCALE) { in visitADD()
2514 (N0.getOperand(1).getOpcode() == ISD::VSCALE) && in visitADD()
2515 (N1.getOpcode() == ISD::VSCALE)) { in visitADD()
3565 if (N1.getOpcode() == ISD::VSCALE) { in visitSUB()
3944 if (N0.getOpcode() == ISD::VSCALE) in visitMUL()
8458 if (N0.getOpcode() == ISD::VSCALE) in visitSHL()
H A DLegalizeIntegerTypes.cpp96 case ISD::VSCALE: Res = PromoteIntRes_VSCALE(N); break; in PromoteIntegerResult()
2251 case ISD::VSCALE: in ExpandIntegerResult()
H A DSelectionDAG.cpp5048 case ISD::VSCALE: in getNode()
5620 if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) { in getNode()
5682 if (N2C && (N1.getOpcode() == ISD::VSCALE) && Flags.hasNoSignedWrap()) { in getNode()
H A DSelectionDAGBuilder.cpp3940 ISD::VSCALE, dl, VScaleTy, in visitGetElementPtr()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp413 setOperationAction(ISD::VSCALE, XLenVT, Custom); in RISCVTargetLowering()
2264 case ISD::VSCALE: { in LowerOperation()
4023 SlideupAmt = DAG.getNode(ISD::VSCALE, DL, XLenVT, SlideupAmt); in lowerINSERT_SUBVECTOR()
4030 VL = DAG.getNode(ISD::VSCALE, DL, XLenVT, VL); in lowerINSERT_SUBVECTOR()
4157 SlidedownAmt = DAG.getNode(ISD::VSCALE, DL, XLenVT, SlidedownAmt); in lowerEXTRACT_SUBVECTOR()
4259 SDValue VLMax = DAG.getNode(ISD::VSCALE, DL, XLenVT, in lowerVECTOR_REVERSE()
7717 Offset = DAG.getNode(ISD::VSCALE, DL, XLenVT, Offset); in LowerFormalArguments()
8007 Offset = DAG.getNode(ISD::VSCALE, DL, XLenVT, Offset); in LowerCall()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td334 def vscale : SDNode<"ISD::VSCALE" , SDTIntUnaryOp, []>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp4998 if (VScale.getOpcode() != ISD::VSCALE) in SelectAddrModeIndexedSVE()
H A DAArch64ISelLowering.cpp1138 setOperationAction(ISD::VSCALE, MVT::i32, Custom); in AArch64TargetLowering()
4925 case ISD::VSCALE: in LowerOperation()