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Searched refs:VOffset (Results 1 – 8 of 8) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp3704 getConstantVRegValWithLookThrough(VOffset, MRI); in updateBufferMMO()
3839 Register VOffset = MI.getOperand(3 + OpOffset).getReg(); in legalizeBufferStore() local
3850 std::tie(VOffset, ImmOffset) = splitBufferOffsets(B, VOffset); in legalizeBufferStore()
3851 updateBufferMMO(MMO, VOffset, SOffset, ImmOffset, VIndex, MRI); in legalizeBufferStore()
3878 .addUse(VOffset) // voffset in legalizeBufferStore()
3920 Register VOffset = MI.getOperand(3 + OpOffset).getReg(); in legalizeBufferLoad() local
3937 std::tie(VOffset, ImmOffset) = splitBufferOffsets(B, VOffset); in legalizeBufferLoad()
3979 .addUse(VOffset) // voffset in legalizeBufferLoad()
4119 Register VOffset = MI.getOperand(4 + OpOffset).getReg(); in legalizeBufferAtomic() local
4126 std::tie(VOffset, ImmOffset) = splitBufferOffsets(B, VOffset); in legalizeBufferAtomic()
[all …]
H A DAMDGPULegalizerInfo.h147 void updateBufferMMO(MachineMemOperand *MMO, Register VOffset,
H A DAMDGPUInstructionSelector.cpp2983 MachineOperand &VOffset = MI.getOperand(4); in selectAMDGPU_BUFFER_ATOMIC_FADD() local
2987 bool HasVOffset = !isOperandImmEqual(VOffset, 0, *MRI); in selectAMDGPU_BUFFER_ATOMIC_FADD()
3025 .addReg(VOffset.getReg()) in selectAMDGPU_BUFFER_ATOMIC_FADD()
3032 I.add(VOffset); in selectAMDGPU_BUFFER_ATOMIC_FADD()
3641 if (Register VOffset = matchZeroExtendFromS32(*MRI, PtrBaseOffset)) { in selectGlobalSAddr() local
3646 MIB.addReg(VOffset); in selectGlobalSAddr()
3665 Register VOffset = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in selectGlobalSAddr() local
3667 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::V_MOV_B32_e32), VOffset) in selectGlobalSAddr()
3672 [=](MachineInstrBuilder &MIB) { MIB.addReg(VOffset); }, // voffset in selectGlobalSAddr()
H A DAMDGPURegisterBankInfo.cpp1451 Register VOffset; in applyMappingSBufferLoad() local
1455 VOffset, SOffset, ImmOffset, Alignment); in applyMappingSBufferLoad()
1497 .addUse(VOffset) // voffset in applyMappingSBufferLoad()
1815 Register VOffset = MI.getOperand(3).getReg(); in selectStoreIntrinsic() local
1820 std::tie(VOffset, ImmOffset) = splitBufferOffsets(B, VOffset); in selectStoreIntrinsic()
1822 const bool Offen = !isZero(VOffset, MRI); in selectStoreIntrinsic()
1851 MIB.addUse(VOffset); in selectStoreIntrinsic()
H A DAMDGPUISelDAGToDAG.cpp217 SDValue &VOffset, SDValue &Offset) const;
1861 SDValue &VOffset, in SelectGlobalSAddr() argument
1891 VOffset = SDValue(VMov, 0); in SelectGlobalSAddr()
1920 VOffset = ZextRHS; in SelectGlobalSAddr()
1928 VOffset = ZextLHS; in SelectGlobalSAddr()
1948 VOffset = SDValue(VMov, 0); in SelectGlobalSAddr()
H A DSIISelLowering.cpp6784 static void updateBufferMMO(MachineMemOperand *MMO, SDValue VOffset, in updateBufferMMO() argument
6787 if (!isa<ConstantSDNode>(VOffset) || !isa<ConstantSDNode>(SOffset) || in updateBufferMMO()
6803 MMO->setOffset(cast<ConstantSDNode>(VOffset)->getSExtValue() + in updateBufferMMO()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCodeEmitter.cpp730 unsigned VOffset = 0; in getMachineOpValue() local
749 ++VOffset; in getMachineOpValue()
771 unsigned Offset = HexagonMCInstrInfo::isVector(MCII, MI) ? VOffset in getMachineOpValue()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp38242 int VOffset = V.getOpcode() == X86ISD::PSHUFLW ? 0 : 4; in combineTargetShuffle() local
38246 WordMask[i + VOffset] = VMask[i] + VOffset; in combineTargetShuffle()