Searched refs:VLSHR (Results 1 – 3 of 3) sorted by relevance
190 VLSHR, enumerator
1984 MAKE_CASE(AArch64ISD::VLSHR) in getTargetNodeName()9884 (SecondOpc == AArch64ISD::VSHL || SecondOpc == AArch64ISD::VLSHR)) { in tryLowerToSLI()9889 (FirstOpc == AArch64ISD::VSHL || FirstOpc == AArch64ISD::VLSHR)) { in tryLowerToSLI()9896 bool IsShiftRight = Shift.getOpcode() == AArch64ISD::VLSHR; in tryLowerToSLI()10749 (Op.getOpcode() == ISD::SRA) ? AArch64ISD::VASHR : AArch64ISD::VLSHR; in LowerVectorSRA_SRL_SHL()13338 if (Shift.getOpcode() != AArch64ISD::VLSHR) in performVectorTruncateCombine()15090 N->getOpcode() == AArch64ISD::VLSHR); in performVectorShiftCombine()16687 case AArch64ISD::VLSHR: in PerformDAGCombine()18718 if (ShiftR->getOpcode() != AArch64ISD::VLSHR) in SimplifyDemandedBitsForTargetNode()
503 def AArch64vlshr : SDNode<"AArch64ISD::VLSHR", SDT_AArch64vshift>;