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Searched refs:VGPR0 (Results 1 – 9 of 9) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSILateBranchLowering.cpp85 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
86 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
87 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
88 .addReg(AMDGPU::VGPR0, RegState::Undef) in generateEndPgm()
H A DAMDGPUCallingConv.td31 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
56 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
89 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
122 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
209 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
221 VGPR0, VGPR1, VGPR2, VGPR3, VGPR4, VGPR5, VGPR6, VGPR7,
H A DGCNNSAReassign.cpp146 unsigned MaxReg = MaxNumVGPRs - NumRegs + AMDGPU::VGPR0; in scavengeRegs()
148 for (unsigned Reg = AMDGPU::VGPR0; Reg <= MaxReg; ++Reg) { in scavengeRegs()
H A DSIInsertWaitcnts.cpp97 unsigned VGPR0; member
471 assert(Reg >= RegisterEncoding.VGPR0 && Reg <= RegisterEncoding.VGPRL); in getRegInterval()
472 Result.first = Reg - RegisterEncoding.VGPR0; in getRegInterval()
1598 RegisterEncoding.VGPR0 = TRI->getEncodingValue(AMDGPU::VGPR0); in runOnMachineFunction()
1599 RegisterEncoding.VGPRL = RegisterEncoding.VGPR0 + NumVGPRsMax - 1; in runOnMachineFunction()
H A DAMDGPUCallLowering.cpp678 CCInfo.AllocateReg(AMDGPU::VGPR0); in lowerFormalArguments()
H A DSOPInstructions.td822 // VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
H A DSIRegisterInfo.cpp176 TmpVGPR = AMDGPU::VGPR0; in prepare()
H A DSIISelLowering.cpp1871 Register Reg = AMDGPU::VGPR0; in allocateSpecialEntryInputVGPRs()
1883 Info.setWorkItemIDY(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
1897 Info.setWorkItemIDZ(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
2352 CCInfo.AllocateReg(AMDGPU::VGPR0); in LowerFormalArguments()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp4110 if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1)) in validateVGPRAlign()
4137 auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0); in validateGWS()