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Searched refs:VECTOR_SPLICE (Results 1 – 10 of 10) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h575 VECTOR_SPLICE, enumerator
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp293 case ISD::VECTOR_SPLICE: return "vector_splice"; in getOperationName()
H A DLegalizeDAG.cpp3059 case ISD::VECTOR_SPLICE: { in ExpandNode()
4573 case ISD::VECTOR_SPLICE: { in PromoteNode()
4576 Tmp3 = DAG.getNode(ISD::VECTOR_SPLICE, dl, NVT, Tmp1, Tmp2, in PromoteNode()
H A DLegalizeIntegerTypes.cpp106 case ISD::VECTOR_SPLICE: in PromoteIntegerResult()
4693 return DAG.getNode(ISD::VECTOR_SPLICE, dl, OutVT, V0, V1, N->getOperand(2)); in PromoteIntRes_VECTOR_SPLICE()
H A DLegalizeVectorTypes.cpp954 case ISD::VECTOR_SPLICE: in SplitVectorResult()
H A DTargetLowering.cpp8761 assert(Node->getOpcode() == ISD::VECTOR_SPLICE && "Unexpected opcode!"); in expandVectorSplice()
H A DSelectionDAGBuilder.cpp11135 setValue(&I, DAG.getNode(ISD::VECTOR_SPLICE, DL, VT, V1, V2, in visitVectorSplice()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp904 setTargetDAGCombine(ISD::VECTOR_SPLICE); in AArch64TargetLowering()
1169 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in AArch64TargetLowering()
1293 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in AArch64TargetLowering()
1391 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv2i1, MVT::nxv2i64); in AArch64TargetLowering()
1392 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv4i1, MVT::nxv4i32); in AArch64TargetLowering()
1393 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv8i1, MVT::nxv8i16); in AArch64TargetLowering()
1394 setOperationPromotedToType(ISD::VECTOR_SPLICE, MVT::nxv16i1, MVT::nxv16i8); in AArch64TargetLowering()
1571 setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); in addTypeForFixedLengthSVE()
4977 case ISD::VECTOR_SPLICE: in LowerOperation()
16595 SDValue Splice = DAG.getNode(ISD::VECTOR_SPLICE, DL, ExtIntTy, LHS, RHS, Idx); in performSVESpliceCombine()
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/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp868 setOperationAction(ISD::VECTOR_SPLICE, VT, Expand); in initActions()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td666 def vector_splice : SDNode<"ISD::VECTOR_SPLICE", SDTVecSlice, []>;