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Searched refs:VECTOR_SHUFFLE (Results 1 – 25 of 28) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp1154 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, in getShuffleCost()
1155 {ISD::VECTOR_SHUFFLE, MVT::v2f32, 1}, in getShuffleCost()
1156 {ISD::VECTOR_SHUFFLE, MVT::v2i64, 1}, in getShuffleCost()
1157 {ISD::VECTOR_SHUFFLE, MVT::v2f64, 1}, in getShuffleCost()
1158 {ISD::VECTOR_SHUFFLE, MVT::v4i16, 1}, in getShuffleCost()
1159 {ISD::VECTOR_SHUFFLE, MVT::v8i8, 1}, in getShuffleCost()
1161 {ISD::VECTOR_SHUFFLE, MVT::v4i32, 1}, in getShuffleCost()
1162 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1}, in getShuffleCost()
1163 {ISD::VECTOR_SHUFFLE, MVT::v8i16, 1}, in getShuffleCost()
1175 {ISD::VECTOR_SHUFFLE, MVT::v2i32, 1}, in getShuffleCost()
[all …]
H A DARMISelLowering.cpp183 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addTypeForNEON()
250 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
322 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
431 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in addMVEVectorTypes()
983 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in ARMTargetLowering()
10168 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG, Subtarget); in LowerOperation()
17404 N->getOperand(0).getOpcode() == ISD::VECTOR_SHUFFLE && in PerformMVETruncCombine()
17405 N->getOperand(1).getOpcode() == ISD::VECTOR_SHUFFLE) { in PerformMVETruncCombine()
17434 Op.getOpcode() == ISD::VECTOR_SHUFFLE || in PerformMVETruncCombine()
17688 case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG); in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h563 VECTOR_SHUFFLE, enumerator
H A DSelectionDAGNodes.h1493 : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {}
1538 return N->getOpcode() == ISD::VECTOR_SHUFFLE;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp157 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in WebAssemblyTargetLowering()
194 setOperationAction(ISD::VECTOR_SHUFFLE, T, Custom); in WebAssemblyTargetLowering()
1313 case ISD::VECTOR_SHUFFLE: in LowerOperation()
2468 case ISD::VECTOR_SHUFFLE: in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp81 setOperationAction(ISD::VECTOR_SHUFFLE, ByteV, Legal); in initializeHVXLowering()
82 setOperationAction(ISD::VECTOR_SHUFFLE, ByteW, Legal); in initializeHVXLowering()
136 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteV); in initializeHVXLowering()
191 setPromoteTo(ISD::VECTOR_SHUFFLE, T, ByteW); in initializeHVXLowering()
H A DHexagonISelLowering.cpp1652 ISD::CONCAT_VECTORS, ISD::VECTOR_SHUFFLE, in HexagonTargetLowering()
1754 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i8, Custom); in HexagonTargetLowering()
1755 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); in HexagonTargetLowering()
1756 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); in HexagonTargetLowering()
3181 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
H A DHexagonISelDAGToDAG.cpp910 case ISD::VECTOR_SHUFFLE: return SelectHvxShuffle(N); in Select()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp292 case ISD::VECTOR_SHUFFLE: return "vector_shuffle"; in getOperationName()
H A DDAGCombiner.cpp1717 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); in visit()
18819 if (IndexC && VecOp.getOpcode() == ISD::VECTOR_SHUFFLE) { in visitEXTRACT_VECTOR_ELT()
18853 TLI.isOperationExpand(ISD::VECTOR_SHUFFLE, VecVT)) { in visitEXTRACT_VECTOR_ELT()
21479 if (N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
21480 N0.getOpcode() != ISD::VECTOR_SHUFFLE) { in visitVECTOR_SHUFFLE()
21497 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
21498 N1.getOpcode() == ISD::VECTOR_SHUFFLE && in visitVECTOR_SHUFFLE()
21553 (Op00.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
21554 Op10.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
21555 Op01.getOpcode() == ISD::VECTOR_SHUFFLE || in visitVECTOR_SHUFFLE()
[all …]
H A DSelectionDAG.cpp741 case ISD::VECTOR_SHUFFLE: { in AddNodeIDCustom()
1925 AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops); in getVectorShuffle()
2529 case ISD::VECTOR_SHUFFLE: { in isSplatValue()
2617 case ISD::VECTOR_SHUFFLE: { in getSplatSourceVector()
2810 case ISD::VECTOR_SHUFFLE: { in computeKnownBits()
3721 case ISD::VECTOR_SHUFFLE: { in ComputeNumSignBits()
6100 case ISD::VECTOR_SHUFFLE: in getNode()
H A DLegalizeVectorTypes.cpp66 case ISD::VECTOR_SHUFFLE: R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break; in ScalarizeVectorResult()
951 case ISD::VECTOR_SHUFFLE: in SplitVectorResult()
3001 case ISD::VECTOR_SHUFFLE: in WidenVectorResult()
H A DLegalizeDAG.cpp2985 case ISD::VECTOR_SHUFFLE: { in ExpandNode()
4560 case ISD::VECTOR_SHUFFLE: { in PromoteNode()
H A DTargetLowering.cpp831 case ISD::VECTOR_SHUFFLE: { in SimplifyMultipleUseDemandedBits()
1118 case ISD::VECTOR_SHUFFLE: { in SimplifyDemandedBits()
2715 case ISD::VECTOR_SHUFFLE: { in SimplifyDemandedVectorElts()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp352 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in SystemZTargetLowering()
645 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in SystemZTargetLowering()
4698 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) { in add()
5516 case ISD::VECTOR_SHUFFLE: in LowerOperation()
5766 else if ((Opcode == ISD::VECTOR_SHUFFLE || Opcode == SystemZISD::SPLAT) && in combineExtract()
6111 Op1.getOpcode() == ISD::VECTOR_SHUFFLE && in combineSTORE()
6739 case ISD::VECTOR_SHUFFLE: return combineVECTOR_SHUFFLE(N, DCI); in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp772 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); in PPCTargetLowering()
773 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); in PPCTargetLowering()
848 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); in PPCTargetLowering()
1001 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal); in PPCTargetLowering()
1049 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal); in PPCTargetLowering()
1337 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in PPCTargetLowering()
10878 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
14528 if (Mask[0] >= NumElts && LHS.getOpcode() != ISD::VECTOR_SHUFFLE && in combineVectorShuffle()
14529 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) { in combineVectorShuffle()
14776 case ISD::VECTOR_SHUFFLE: in PerformDAGCombine()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp373 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand); in SITargetLowering()
374 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand); in SITargetLowering()
375 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand); in SITargetLowering()
376 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand); in SITargetLowering()
733 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f16, Custom); in SITargetLowering()
734 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); in SITargetLowering()
4577 case ISD::VECTOR_SHUFFLE: in LowerOperation()
H A DAMDGPUISelLowering.cpp494 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand); in AMDGPUTargetLowering()
529 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand); in AMDGPUTargetLowering()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1829 case ShuffleVector: return ISD::VECTOR_SHUFFLE; in InstructionOpcodeToISD()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp351 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom); in addMSAIntType()
467 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); in LowerOperation()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFragmentsSIMD.td326 // Specific shuffle nodes - At some point ISD::VECTOR_SHUFFLE will always get
H A DX86ISelLowering.cpp991 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
998 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1421 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1506 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
1734 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in X86TargetLowering()
2008 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); in X86TargetLowering()
7535 case ISD::VECTOR_SHUFFLE: { in getFauxShuffleMask()
10413 isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT))) { in LowerBUILD_VECTOR()
38328 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) in isAddSubOrSubAdd()
38381 if (N->getOpcode() != ISD::VECTOR_SHUFFLE) in combineShuffleToFMAddSub()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td664 def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp720 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in RISCVTargetLowering()
791 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); in RISCVTargetLowering()
2513 case ISD::VECTOR_SHUFFLE: in LowerOperation()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp375 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f16, Expand); in NVPTXTargetLowering()

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