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Searched refs:VECREDUCE_AND (Results 1 – 13 of 13) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1235 VECREDUCE_AND, enumerator
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp480 case ISD::VECREDUCE_AND: in LegalizeOp()
884 case ISD::VECREDUCE_AND: in Expand()
H A DSelectionDAGDumper.cpp474 case ISD::VECREDUCE_AND: return "vecreduce_and"; in getOperationName()
H A DLegalizeIntegerTypes.cpp213 case ISD::VECREDUCE_AND: in PromoteIntegerResult()
1556 case ISD::VECREDUCE_AND: in PromoteIntegerOperand()
2033 case ISD::VECREDUCE_AND: in PromoteIntOp_VECREDUCE()
2233 case ISD::VECREDUCE_AND: in ExpandIntegerResult()
H A DLegalizeVectorTypes.cpp654 case ISD::VECREDUCE_AND: in ScalarizeVectorOperand()
2221 case ISD::VECREDUCE_AND: in SplitVectorOperand()
4582 case ISD::VECREDUCE_AND: in WidenVectorOperand()
H A DLegalizeDAG.cpp1171 case ISD::VECREDUCE_AND: in LegalizeOp()
3757 case ISD::VECREDUCE_AND: in ExpandNode()
H A DSelectionDAG.cpp383 case ISD::VECREDUCE_AND: in getVecReduceBaseOpcode()
5068 return getNode(ISD::VECREDUCE_AND, DL, VT, Operand); in getNode()
H A DDAGCombiner.cpp1732 case ISD::VECREDUCE_AND: in visit()
21853 if (Opcode == ISD::VECREDUCE_AND || Opcode == ISD::VECREDUCE_OR) { in visitVECREDUCE()
21854 unsigned NewOpcode = Opcode == ISD::VECREDUCE_AND in visitVECREDUCE()
H A DSelectionDAGBuilder.cpp9355 Res = DAG.getNode(ISD::VECREDUCE_AND, dl, VT, Op1); in visitVectorReduce()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp445 setOperationAction(ISD::VECREDUCE_AND, MVT::i64, Custom); in RISCVTargetLowering()
470 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in RISCVTargetLowering()
535 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in RISCVTargetLowering()
694 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in RISCVTargetLowering()
2488 case ISD::VECREDUCE_AND: in LowerOperation()
3738 case ISD::VECREDUCE_AND: in getRVVReductionOp()
3752 assert((Op.getOpcode() == ISD::VECREDUCE_AND || in lowerVectorMaskVECREDUCE()
3774 case ISD::VECREDUCE_AND: in lowerVectorMaskVECREDUCE()
5347 case ISD::VECREDUCE_AND: in ReplaceNodeResults()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp855 setOperationAction(ISD::VECREDUCE_AND, VT, Expand); in initActions()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1183 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1215 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1376 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in AArch64TargetLowering()
1582 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in addTypeForFixedLengthSVE()
4908 case ISD::VECREDUCE_AND: in LowerOperation()
10951 bool OverrideNEON = Op.getOpcode() == ISD::VECREDUCE_AND || in LowerVECREDUCE()
10966 case ISD::VECREDUCE_AND: in LowerVECREDUCE()
18344 case ISD::VECREDUCE_AND: { in LowerPredReductionToSVE()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp294 setOperationAction(ISD::VECREDUCE_AND, VT, Custom); in addMVEVectorTypes()
9935 case ISD::VECREDUCE_AND: BaseOpcode = ISD::AND; break; in LowerVecReduce()
10207 case ISD::VECREDUCE_AND: in LowerOperation()