Searched refs:VCVT (Results 1 – 10 of 10) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86SchedSkylakeServer.td | 1896 "VCVT(T?)PD2QQ(Z|Z256)rm(b?)", 1897 "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)", 1898 "VCVT(T?)PS2DQYrm", 1899 "VCVT(T?)PS2DQ(Z|Z256)rm(b?)", 1900 "VCVT(T?)PS2QQZ256rm(b?)", 1901 "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)", 1902 "VCVT(T?)PS2UQQZ256rm(b?)", 1998 def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)", 1999 "VCVT(T?)SS2USI64Zrm(b?)")>; 2006 def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)", [all …]
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| H A D | X86ScheduleZnver2.td | 1313 def : InstRW<[Zn2WriteCVTPD2DQr], (instregex "VCVT(T?)PD2DQYrr")>; 1315 def : InstRW<[Zn2WriteCVTPD2DQLd], (instregex "VCVT(T?)PD2DQYrm")>;
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| H A D | X86ScheduleZnver1.td | 1316 def : InstRW<[ZnWriteCVTPD2DQr], (instregex "VCVT(T?)PD2DQYrr")>; 1318 def : InstRW<[ZnWriteCVTPD2DQLd], (instregex "VCVT(T?)PD2DQYrm")>;
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleA57.td | 734 "VCVT(A|N|P|M)(SH|UH|SS|US|SD|UD)", "VCVT(BDH|THD|TDH)")>; 1161 "VCVT(f2sd|f2ud|s2fd|u2fd|f2sq|f2uq|s2fq|u2fq|f2xsd|f2xud|xs2fd|xu2fd)", 1162 "VCVT(f2xsq|f2xuq|xs2fq|xu2fq)", 1163 "VCVT(AN|MN|NN|PN)(SDf|SQf|UDf|UQf|SDh|SQh|UDh|UQh)")>; 1167 "VCVT(h2sd|h2ud|s2hd|u2hd|h2sq|h2uq|s2hq|u2hq|h2xsd|h2xud|xs2hd|xu2hd)", 1168 "VCVT(h2xsq|h2xuq|xs2hq|xu2hq)", 1169 "VCVT(f2h|h2f)")>;
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| H A D | ARMScheduleSwift.td | 623 def : InstRW<[SwiftWriteP1FourCycle], (instregex "VCVT", "V(S|U)IT", "VTO(S|U)")>;
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| H A D | ARMScheduleR52.td | 796 (instregex "VCVT", "VSITO", "VUITO", "VTO")>;
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| H A D | ARMInstrNEON.td | 6794 // VCVT : Vector Convert Between Floating-Point and Integers 6839 // VCVT{A, N, P, M} 6871 // VCVT : Vector Convert Between Floating-Point and Fixed-Point. 6951 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
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| H A D | ARMInstrVFP.td | 131 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
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| H A D | ARMISelLowering.cpp | 7844 if (SDValue VCVT = LowerBuildVectorOfFPTrunc(Op, DAG, Subtarget)) in LowerBUILD_VECTOR() local 7845 return VCVT; in LowerBUILD_VECTOR() 7846 if (SDValue VCVT = LowerBuildVectorOfFPExt(Op, DAG, Subtarget)) in LowerBUILD_VECTOR() local 7847 return VCVT; in LowerBUILD_VECTOR()
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| H A D | ARMInstrMVE.td | 4039 // The unsuffixed VCVT for float->int implicitly rounds toward zero, 4045 // Whereas VCVT for int->float rounds to nearest
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