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Searched refs:UMLAL (Results 1 – 10 of 10) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h264 UMLAL, // 64bit Unsigned Accumulate Multiply enumerator
H A DARMScheduleSwift.td307 (instregex "SMLAL", "UMLAL", "SMLALBT",
H A DARMScheduleR52.td279 "SMLAL", "UMLAL", "SMLALBT",
H A DARMInstrInfo.td4392 def UMLAL : AsMla1I64<0b0000101, (outs GPR:$RdLo, GPR:$RdHi),
4426 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
6375 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
6389 (UMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
H A DARMISelDAGToDAG.cpp3909 case ARMISD::UMLAL:{ in Select()
3923 Subtarget->hasV6Ops() ? ARM::UMLAL : ARM::UMLALv5, dl, in Select()
H A DARMScheduleA9.td2551 (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL",
H A DARMISelLowering.cpp1762 MAKE_CASE(ARMISD::UMLAL) in getTargetNodeName()
12530 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL; in AddCombineTo64bitMLAL()
12637 if (AddcNode->getOperand(0).getOpcode() == ARMISD::UMLAL) { in AddCombineTo64bitUMAAL()
12640 } else if (AddcNode->getOperand(1).getOpcode() == ARMISD::UMLAL) { in AddCombineTo64bitUMAAL()
17665 case ARMISD::UMLAL: return PerformUMLALCombine(N, DCI.DAG, Subtarget); in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td526 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
H A DAArch64InstrInfo.td4967 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
5050 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
6246 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp8263 case ARM::UMLAL: in validateInstruction()