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Searched refs:UINT_TO_FP (Results 1 – 25 of 34) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1573 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i64, 1 }, in getCastInstrCost()
1574 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 1 }, in getCastInstrCost()
1682 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i1, 4 }, in getCastInstrCost()
1683 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i1, 3 }, in getCastInstrCost()
1684 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v16i8, 2 }, in getCastInstrCost()
1685 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i8, 1 }, in getCastInstrCost()
1686 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i16, 2 }, in getCastInstrCost()
1687 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i16, 1 }, in getCastInstrCost()
1688 { ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i32, 1 }, in getCastInstrCost()
1689 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 1 }, in getCastInstrCost()
[all …]
H A DX86IntrinsicsInfo.h918 X86_INTRINSIC_DATA(avx512_uitofp_round, INTR_TYPE_1OP, ISD::UINT_TO_FP, X86ISD::UINT_TO_FP_RND),
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMTargetTransformInfo.cpp612 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
698 { ISD::UINT_TO_FP, MVT::f32, MVT::i1, 2 }, in getCastInstrCost()
700 { ISD::UINT_TO_FP, MVT::f64, MVT::i1, 2 }, in getCastInstrCost()
702 { ISD::UINT_TO_FP, MVT::f32, MVT::i8, 2 }, in getCastInstrCost()
704 { ISD::UINT_TO_FP, MVT::f64, MVT::i8, 2 }, in getCastInstrCost()
706 { ISD::UINT_TO_FP, MVT::f32, MVT::i16, 2 }, in getCastInstrCost()
708 { ISD::UINT_TO_FP, MVT::f64, MVT::i16, 2 }, in getCastInstrCost()
710 { ISD::UINT_TO_FP, MVT::f32, MVT::i32, 2 }, in getCastInstrCost()
712 { ISD::UINT_TO_FP, MVT::f64, MVT::i32, 2 }, in getCastInstrCost()
714 { ISD::UINT_TO_FP, MVT::f32, MVT::i64, 10 }, in getCastInstrCost()
[all …]
H A DARMISelLowering.cpp173 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in addTypeForNEON()
178 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in addTypeForNEON()
300 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in addMVEVectorTypes()
907 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); in ARMTargetLowering()
908 setOperationAction(ISD::UINT_TO_FP, MVT::v8i16, Custom); in ARMTargetLowering()
1038 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in ARMTargetLowering()
5849 case ISD::UINT_TO_FP: in LowerVectorINT_TO_FP()
5851 Opc = ISD::UINT_TO_FP; in LowerVectorINT_TO_FP()
10138 case ISD::UINT_TO_FP: return LowerINT_TO_FP(Op, DAG); in LowerOperation()
14730 Ext->use_begin()->getOpcode() == ISD::UINT_TO_FP)) in PerformExtractEltToVMOVRRD()
[all …]
H A DARMISelDAGToDAG.cpp3178 if (VecVal->getOpcode() == ISD::UINT_TO_FP || in transformFixedFloatingPointConversion()
3318 if (LHS.getOpcode() != ISD::SINT_TO_FP && LHS.getOpcode() != ISD::UINT_TO_FP) in tryFMULFixed()
3322 N, N, LHS.getOpcode() == ISD::UINT_TO_FP, true); in tryFMULFixed()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64TargetTransformInfo.cpp994 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, in getCastInstrCost()
995 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 }, in getCastInstrCost()
996 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i64, 1 }, in getCastInstrCost()
1002 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i8, 3 }, in getCastInstrCost()
1003 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i16, 3 }, in getCastInstrCost()
1004 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i64, 2 }, in getCastInstrCost()
1009 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 }, in getCastInstrCost()
1010 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
1016 { ISD::UINT_TO_FP, MVT::v8f32, MVT::v8i16, 4 }, in getCastInstrCost()
1026 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i8, 4 }, in getCastInstrCost()
[all …]
H A DAArch64ISelLowering.cpp468 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in AArch64TargetLowering()
469 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in AArch64TargetLowering()
470 setOperationAction(ISD::UINT_TO_FP, MVT::i128, Custom); in AArch64TargetLowering()
889 setTargetDAGCombine(ISD::UINT_TO_FP); in AArch64TargetLowering()
997 setOperationAction(ISD::UINT_TO_FP, MVT::v1i64, Expand); in AArch64TargetLowering()
1158 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in AArch64TargetLowering()
1226 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in AArch64TargetLowering()
1578 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in addTypeForFixedLengthSVE()
4869 case ISD::UINT_TO_FP: in LowerOperation()
12895 (Opc != ISD::SINT_TO_FP && Opc != ISD::UINT_TO_FP)) in performFDivCombine()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/IR/
H A DConstrainedOps.def59 DAG_INSTRUCTION(UIToFP, 1, 1, experimental_constrained_uitofp, UINT_TO_FP)
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h740 UINT_TO_FP, enumerator
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp477 case ISD::UINT_TO_FP: in LegalizeOp()
577 case ISD::UINT_TO_FP: in Promote()
649 unsigned Opc = (Node->getOpcode() == ISD::UINT_TO_FP || in PromoteINT_TO_FP()
764 case ISD::UINT_TO_FP: in Expand()
H A DSelectionDAGDumper.cpp350 case ISD::UINT_TO_FP: return "uint_to_fp"; in getOperationName()
H A DLegalizeDAG.cpp1004 case ISD::UINT_TO_FP: in LegalizeOp()
2506 unsigned UIntOp = IsStrict ? ISD::STRICT_UINT_TO_FP : ISD::UINT_TO_FP; in PromoteLegalINT_TO_FP()
2906 case ISD::UINT_TO_FP: in ExpandNode()
4154 case ISD::UINT_TO_FP: { in ConvertNodeToLibcall()
4364 if (Node->getOpcode() == ISD::UINT_TO_FP || in PromoteNode()
4439 case ISD::UINT_TO_FP: in PromoteNode()
H A DLegalizeFloatTypes.cpp137 case ISD::UINT_TO_FP: R = SoftenFloatRes_XINT_TO_FP(N); break; in SoftenFloatResult()
1253 case ISD::UINT_TO_FP: ExpandFloatRes_XINT_TO_FP(N, Lo, Hi); break; in ExpandFloatResult()
2274 case ISD::UINT_TO_FP: R = PromoteFloatRes_XINT_TO_FP(N); break; in PromoteFloatResult()
2637 case ISD::UINT_TO_FP: R = SoftPromoteHalfRes_XINT_TO_FP(N); break; in SoftPromoteHalfResult()
H A DLegalizeVectorTypes.cpp106 case ISD::UINT_TO_FP: in ScalarizeVectorResult()
614 case ISD::UINT_TO_FP: in ScalarizeVectorOperand()
1000 case ISD::UINT_TO_FP: in SplitVectorResult()
2187 case ISD::UINT_TO_FP: in SplitVectorOperand()
3100 case ISD::UINT_TO_FP: in WidenVectorResult()
4567 case ISD::UINT_TO_FP: in WidenVectorOperand()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp166 setTargetDAGCombine(ISD::UINT_TO_FP); in WebAssemblyTargetLowering()
241 {ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::FP_TO_SINT, ISD::FP_TO_UINT}) in WebAssemblyTargetLowering()
2242 case ISD::UINT_TO_FP: in performVectorConvertLowCombine()
2269 case ISD::UINT_TO_FP: in performVectorConvertLowCombine()
2312 case ISD::UINT_TO_FP: in performVectorConvertLowCombine()
2474 case ISD::UINT_TO_FP: in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp441 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in AMDGPUTargetLowering()
477 setOperationAction(ISD::UINT_TO_FP, VT, Expand); in AMDGPUTargetLowering()
1305 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); in LowerOperation()
1734 ISD::NodeType ToFp = Sign ? ISD::SINT_TO_FP : ISD::UINT_TO_FP; in LowerDIVREM24()
1869 SDValue Cvt_Lo = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Lo); in LowerUDIVREM64()
1870 SDValue Cvt_Hi = DAG.getNode(ISD::UINT_TO_FP, DL, MVT::f32, RHS_Hi); in LowerUDIVREM64()
2551 SDValue CvtHi = DAG.getNode(Signed ? ISD::SINT_TO_FP : ISD::UINT_TO_FP, in LowerINT_TO_FP64()
2554 SDValue CvtLo = DAG.getNode(ISD::UINT_TO_FP, SL, MVT::f64, Lo); in LowerINT_TO_FP64()
2576 return DAG.getNode(ISD::UINT_TO_FP, DL, DestVT, Ext); in LowerUINT_TO_FP()
H A DR600ISelLowering.cpp1762 if (Arg.getOpcode() == ISD::UINT_TO_FP && Arg.getValueType() == MVT::f64) { in PerformDAGCombine()
1763 return DAG.getNode(ISD::UINT_TO_FP, DL, N->getValueType(0), in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp247 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1, in PPCTargetLowering()
267 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom); in PPCTargetLowering()
493 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Legal); in PPCTargetLowering()
507 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); in PPCTargetLowering()
1321 setTargetDAGCombine(ISD::UINT_TO_FP); in PPCTargetLowering()
8298 UI->getOpcode() != ISD::UINT_TO_FP && in directMoveIsProfitable()
10864 case ISD::UINT_TO_FP: in LowerOperation()
14056 FirstInput.getOpcode() != ISD::UINT_TO_FP) in DAGCombineBuildVector()
14059 N->getOperand(1).getOpcode() != ISD::UINT_TO_FP) in DAGCombineBuildVector()
14098 N->getOpcode() == ISD::UINT_TO_FP) && in combineFPToIntToFP()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp207 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); // use i64 in initSPUActions()
209 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in initSPUActions()
2487 case ISD::UINT_TO_FP: in isI32Insn()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp268 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote); in SystemZTargetLowering()
269 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); in SystemZTargetLowering()
413 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal); in SystemZTargetLowering()
414 setOperationAction(ISD::UINT_TO_FP, MVT::v2f64, Legal); in SystemZTargetLowering()
433 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal); in SystemZTargetLowering()
434 setOperationAction(ISD::UINT_TO_FP, MVT::v4f32, Legal); in SystemZTargetLowering()
651 setTargetDAGCombine(ISD::UINT_TO_FP); in SystemZTargetLowering()
6384 (Opcode == ISD::UINT_TO_FP ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND); in combineINT_TO_FP()
6747 case ISD::UINT_TO_FP: return combineINT_TO_FP(N, DCI); in PerformDAGCombine()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1520 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); in SparcTargetLowering()
1522 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); in SparcTargetLowering()
3036 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this, in LowerOperation()
3383 case ISD::UINT_TO_FP: in ReplaceNodeResults()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1773 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote); in HexagonTargetLowering()
1774 setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); in HexagonTargetLowering()
1775 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote); in HexagonTargetLowering()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp479 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in RISCVTargetLowering()
515 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in RISCVTargetLowering()
699 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in RISCVTargetLowering()
2382 case ISD::UINT_TO_FP: { in LowerOperation()
2406 unsigned ExtOpcode = Op.getOpcode() == ISD::UINT_TO_FP in LowerOperation()
2459 case ISD::UINT_TO_FP: in LowerOperation()
/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1811 case UIToFP: return ISD::UINT_TO_FP; in InstructionOpcodeToISD()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp359 setOperationAction(ISD::UINT_TO_FP, Ty, Legal); in addMSAIntType()
1871 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()

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