Home
last modified time | relevance | path

Searched refs:TruePred (Results 1 – 8 of 8) sorted by relevance

/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedPredExynos.td53 MCReturnStatement<TruePred>>,
56 MCReturnStatement<TruePred>>],
69 MCReturnStatement<TruePred>>,
72 MCReturnStatement<TruePred>>],
90 MCReturnStatement<TruePred>>,
93 MCReturnStatement<TruePred>>],
128 MCReturnStatement<TruePred>>,
154 MCReturnStatement<TruePred>>],
/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombinePHI.cpp1255 BasicBlock *TruePred = nullptr, *FalsePred = nullptr; in SimplifyUsingControlFlow() local
1259 TruePred = Pred; in SimplifyUsingControlFlow()
1263 assert(TruePred && FalsePred && "Must be!"); in SimplifyUsingControlFlow()
1277 BasicBlockEdge TrueIncEdge(TruePred, BB); in SimplifyUsingControlFlow()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ScheduleBdVer2.td1343 SchedVar<MCSchedPredicate<TruePred>, [WriteALU]>
1350 SchedVar<MCSchedPredicate<TruePred>, [WriteFLogic]>
1361 SchedVar<MCSchedPredicate<TruePred>, [WriteVecLogic]>
1367 SchedVar<MCSchedPredicate<TruePred>, [WriteVecLogicX]>
1374 SchedVar<MCSchedPredicate<TruePred>, [WriteVecALU]>
1384 SchedVar<MCSchedPredicate<TruePred>, [WriteVecALUX]>
H A DX86ScheduleBtVer2.td1048 ], TruePred >
H A DX86ScheduleZnver3.td1516 ], TruePred >
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetInstrPredicate.td78 def TruePred : MCTrue;
154 // Otherwise, it simply evaluates to TruePred.
H A DTargetSchedule.td381 def NoSchedPred : MCSchedPredicate<TruePred>;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DSimplifyCFG.cpp3398 BasicBlock *TruePred = QTB ? QTB : QFB->getSinglePredecessor(); in mergeConditionalStoreToAddress() local
3400 SplitBlockPredecessors(PostBB, {QFB, TruePred}, "condstore.split", DTU); in mergeConditionalStoreToAddress()