| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 108 const TargetRegisterClass *getPointerRegClass(
171 bool hasVGPRs(const TargetRegisterClass *RC) const;
182 const TargetRegisterClass *
186 const TargetRegisterClass *
190 const TargetRegisterClass *
196 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
203 const TargetRegisterClass *
262 const TargetRegisterClass *
267 const TargetRegisterClass *
274 const TargetRegisterClass *
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| H A D | SIRegisterInfo.cpp | 1976 const TargetRegisterClass *
2036 const TargetRegisterClass *
2046 const TargetRegisterClass *
2076 const TargetRegisterClass *
2183 const TargetRegisterClass *
2191 const TargetRegisterClass *
2199 const TargetRegisterClass *
2230 const TargetRegisterClass *
2314 const TargetRegisterClass*
2403 const TargetRegisterClass *
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| H A D | SIFixSGPRCopies.cpp | 140 static std::pair<const TargetRegisterClass *, const TargetRegisterClass *>
147 const TargetRegisterClass *SrcRC = SrcReg.isVirtual() in getCopyRegClasses()
154 const TargetRegisterClass *DstRC = DstReg.isVirtual() in getCopyRegClasses()
161 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, in isVGPRToSGPRCopy()
162 const TargetRegisterClass *DstRC, in isVGPRToSGPRCopy()
168 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, in isSGPRToVGPRCopy()
237 const TargetRegisterClass *SrcRC, *DstRC; in foldVGPRCopyIntoRegSequence()
589 const TargetRegisterClass *SrcRC, *DstRC; in runOnMachineFunction()
684 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; in runOnMachineFunction()
812 const TargetRegisterClass *OpRC = in processPHINode()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 46 class TargetRegisterClass {
339 const TargetRegisterClass *
585 virtual const TargetRegisterClass *
610 virtual const TargetRegisterClass *
710 const TargetRegisterClass*
749 const TargetRegisterClass *
756 virtual const TargetRegisterClass *
765 virtual const TargetRegisterClass *
774 virtual const TargetRegisterClass *
804 const TargetRegisterClass *RC) const = 0;
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| H A D | RegisterClassInfo.h | 73 void compute(const TargetRegisterClass *RC) const;
76 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
92 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
99 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
109 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
125 uint8_t getMinCost(const TargetRegisterClass *RC) const { in getMinCost()
133 unsigned getLastCostChange(const TargetRegisterClass *RC) const { in getLastCostChange()
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| H A D | RegisterScavenging.h | 31 class TargetRegisterClass; variable
116 BitVector getRegsAvailable(const TargetRegisterClass *RC);
120 Register FindUnusedReg(const TargetRegisterClass *RC) const;
154 Register scavengeRegister(const TargetRegisterClass *RC,
157 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
171 Register scavengeRegisterBackwards(const TargetRegisterClass &RC,
219 ScavengedInfo &spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
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| H A D | LiveStacks.h | 28 class TargetRegisterClass; variable
43 std::map<int, const TargetRegisterClass *> S2RCMap;
62 LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
80 const TargetRegisterClass *getIntervalRegClass(int Slot) const { in getIntervalRegClass()
82 std::map<int, const TargetRegisterClass *>::const_iterator I = in getIntervalRegClass()
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| H A D | RegAllocCommon.h | 17 class TargetRegisterClass; variable
21 const TargetRegisterClass &RC)> RegClassFilterFunc;
26 const TargetRegisterClass &) { in allocateAllRegClasses() argument
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| H A D | FastISel.h | 56 class TargetRegisterClass; variable
384 const TargetRegisterClass *RC);
389 const TargetRegisterClass *RC, unsigned Op0);
394 const TargetRegisterClass *RC, unsigned Op0,
400 const TargetRegisterClass *RC, unsigned Op0,
406 const TargetRegisterClass *RC, unsigned Op0,
412 const TargetRegisterClass *RC, unsigned Op0,
418 const TargetRegisterClass *RC,
424 const TargetRegisterClass *RC, unsigned Op0,
430 const TargetRegisterClass *RC, uint64_t Imm);
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86RegisterInfo.h | 60 const TargetRegisterClass *
61 getMatchingSuperRegClass(const TargetRegisterClass *A,
62 const TargetRegisterClass *B,
65 const TargetRegisterClass *
66 getSubClassWithSubReg(const TargetRegisterClass *RC,
69 const TargetRegisterClass *
70 getLargestLegalSuperClass(const TargetRegisterClass *RC,
73 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
80 const TargetRegisterClass *
87 const TargetRegisterClass *
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| H A D | X86RegisterInfo.cpp | 82 const TargetRegisterClass *
83 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, in getSubClassWithSubReg()
94 const TargetRegisterClass *
107 const TargetRegisterClass *
123 const TargetRegisterClass *Super = RC; in getLargestLegalSuperClass()
124 TargetRegisterClass::sc_iterator I = RC->getSuperClasses(); in getLargestLegalSuperClass()
174 const TargetRegisterClass *
230 const TargetRegisterClass *
244 const TargetRegisterClass *
256 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, in getRegPressureLimit()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | TargetRegisterInfo.cpp | 193 const TargetRegisterClass *
210 const TargetRegisterClass *
217 const TargetRegisterClass* BestRC = nullptr; in getMinimalPhysRegClass()
228 const TargetRegisterClass *
235 const TargetRegisterClass *BestRC = nullptr; in getMinimalPhysRegClassLLT()
287 const TargetRegisterClass *
301 const TargetRegisterClass *
317 const TargetRegisterClass *TargetRegisterInfo::
335 const TargetRegisterClass *BestRC = nullptr; in getCommonSuperRegClass()
352 const TargetRegisterClass *RC = in getCommonSuperRegClass()
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| H A D | CriticalAntiDepBreaker.cpp | 72 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
90 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
120 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in Observe()
127 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in Observe()
187 const TargetRegisterClass *NewRC = nullptr; in PrescanInstruction()
197 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
207 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in PrescanInstruction()
315 const TargetRegisterClass *NewRC = nullptr; in ScanInstruction()
324 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in ScanInstruction()
400 const TargetRegisterClass *RC, in findSuitableFreeRegister()
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| H A D | MachineRegisterInfo.cpp | 68 static const TargetRegisterClass *
70 const TargetRegisterClass *OldRC, in constrainRegClass()
74 const TargetRegisterClass *NewRC = in constrainRegClass()
84 const TargetRegisterClass *
105 else if (RegCB.is<const TargetRegisterClass *>() != in constrainRegAttrs()
106 ConstrainingRegCB.is<const TargetRegisterClass *>()) in constrainRegAttrs()
108 else if (RegCB.is<const TargetRegisterClass *>()) { in constrainRegAttrs()
110 *this, Reg, RegCB.get<const TargetRegisterClass *>(), in constrainRegAttrs()
124 const TargetRegisterClass *OldRC = getRegClass(Reg); in recomputeRegClass()
125 const TargetRegisterClass *NewRC = in recomputeRegClass()
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| H A D | RegisterCoalescer.h | 22 class TargetRegisterClass; variable
57 const TargetRegisterClass *NewRC = nullptr;
109 const TargetRegisterClass *getNewRC() const { return NewRC; } in getNewRC()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterInfo.h | 23 class TargetRegisterClass; variable
64 const TargetRegisterClass *
65 getSubClassWithSubReg(const TargetRegisterClass *RC,
97 const TargetRegisterClass *
100 const TargetRegisterClass *
101 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
126 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
133 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
134 unsigned SubReg, const TargetRegisterClass *DstRC,
135 unsigned DstSubReg, const TargetRegisterClass *NewRC,
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseRegisterInfo.h | 144 const TargetRegisterClass *
147 const TargetRegisterClass *
148 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
150 const TargetRegisterClass *
151 getLargestLegalSuperClass(const TargetRegisterClass *RC,
154 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
206 const TargetRegisterClass *SrcRC,
208 const TargetRegisterClass *DstRC,
210 const TargetRegisterClass *NewRC,
213 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.h | 35 const TargetRegisterClass *
36 getLargestLegalSuperClass(const TargetRegisterClass *RC,
46 const TargetRegisterClass *
55 const TargetRegisterClass *SrcRC,
57 const TargetRegisterClass *DstRC,
59 const TargetRegisterClass *NewRC,
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.h | 59 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
60 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
61 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
69 unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
73 const TargetRegisterClass *RC) const;
77 const TargetRegisterClass *
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| H A D | HexagonVLIWPacketizer.h | 25 class TargetRegisterClass; variable
120 const TargetRegisterClass *RC);
123 const TargetRegisterClass *RC);
128 const TargetRegisterClass *RC);
131 const TargetRegisterClass *RC);
143 bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kRegisterInfo.h | 60 const TargetRegisterClass *
69 const TargetRegisterClass *RC) const;
74 const TargetRegisterClass *getMaximalPhysRegClass(unsigned reg, MVT VT) const;
77 int getRegisterOrder(unsigned Reg, const TargetRegisterClass &TRC) const;
104 const TargetRegisterClass *intRegClass(unsigned Size) const;
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| H A D | M68kRegisterInfo.cpp | 69 const TargetRegisterClass *
76 const TargetRegisterClass *RC) const { in getMatchingMegaReg()
83 const TargetRegisterClass *
90 const TargetRegisterClass *BestRC = nullptr; in getMaximalPhysRegClass()
93 const TargetRegisterClass *RC = *I; in getMaximalPhysRegClass()
106 const TargetRegisterClass &TRC) const { in getRegisterOrder()
265 const TargetRegisterClass *M68kRegisterInfo::intRegClass(unsigned size) const { in intRegClass()
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZRegisterInfo.h | 124 const TargetRegisterClass *
133 const TargetRegisterClass *
134 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
158 const TargetRegisterClass *SrcRC,
160 const TargetRegisterClass *DstRC,
162 const TargetRegisterClass *NewRC,
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterInfo.h | 25 class TargetRegisterClass; variable
47 const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
50 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
73 virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegisterBank.cpp | 35 const TargetRegisterClass &RC = *TRI.getRegClass(RCId); in verify()
46 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId); in verify()
61 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers()
105 const TargetRegisterClass &RC = *TRI->getRegClass(RCId); in print()
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