Searched refs:TargetLo (Results 1 – 2 of 2) sorted by relevance
172 Register TargetLo = TRI->getSubReg(TargetReg, AMDGPU::sub0); in buildGitPtr() local186 BuildMI(MBB, I, DL, SMovB32, TargetLo) in buildGitPtr()
15444 bool TargetLo = LoInputs.size() >= HiInputs.size(); in lowerV16I8Shuffle() local15445 ArrayRef<int> InPlaceInputs = TargetLo ? LoInputs : HiInputs; in lowerV16I8Shuffle()15446 ArrayRef<int> MovingInputs = TargetLo ? HiInputs : LoInputs; in lowerV16I8Shuffle()15454 int j = TargetLo ? 0 : 4, je = j + 4; in lowerV16I8Shuffle()15488 V1 = DAG.getNode(TargetLo ? X86ISD::UNPCKL : X86ISD::UNPCKH, DL, in lowerV16I8Shuffle()15495 int MappedMask = LaneMap[Mask[i]] - (TargetLo ? 0 : 8); in lowerV16I8Shuffle()