Searched refs:SubVecVT (Results 1 – 10 of 10) sorted by relevance
| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 3906 MVT SubVecVT = SubVec.getSimpleValueType(); in lowerINSERT_SUBVECTOR() local 3921 SubVecVT.getVectorMinNumElements() >= 8) { in lowerINSERT_SUBVECTOR() 3927 SubVecVT = in lowerINSERT_SUBVECTOR() 3933 SubVec = DAG.getBitcast(SubVecVT, SubVec); in lowerINSERT_SUBVECTOR() 3955 if (SubVecVT.isFixedLengthVector()) { in lowerINSERT_SUBVECTOR() 3983 VecVT, SubVecVT, OrigIdx, TRI); in lowerINSERT_SUBVECTOR() 4054 MVT SubVecVT = Op.getSimpleValueType(); in lowerEXTRACT_SUBVECTOR() local 4069 SubVecVT.getVectorMinNumElements() >= 8) { in lowerEXTRACT_SUBVECTOR() 4075 SubVecVT = in lowerEXTRACT_SUBVECTOR() 4104 if (SubVecVT.isFixedLengthVector()) { in lowerEXTRACT_SUBVECTOR() [all …]
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| H A D | RISCVISelDAGToDAG.cpp | 1262 MVT SubVecVT = SubV.getSimpleValueType(); in Select() local 1265 MVT SubVecContainerVT = SubVecVT; in Select() 1267 if (SubVecVT.isFixedLengthVector()) in Select() 1268 SubVecContainerVT = TLI.getContainerForFixedLengthVector(SubVecVT); in Select()
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| H A D | RISCVISelLowering.h | 495 decomposeSubvectorInsertExtractToSubRegs(MVT VecVT, MVT SubVecVT,
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 1281 EVT SubVecVT = SubVec.getValueType(); in SplitVecRes_INSERT_SUBVECTOR() local 1283 unsigned SubElems = SubVecVT.getVectorMinNumElements(); in SplitVecRes_INSERT_SUBVECTOR() 1297 if (VecVT.isScalableVector() == SubVecVT.isScalableVector() && in SplitVecRes_INSERT_SUBVECTOR() 1319 TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, SubVecVT, Idx); in SplitVecRes_INSERT_SUBVECTOR()
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| H A D | TargetLowering.cpp | 7847 EVT SubVecVT, in getVectorSubVecPointer() argument 7861 if (SubVecVT.isFixedLengthVector()) { in getVectorSubVecPointer() 7862 assert(SubVecVT.getVectorElementType() == EltVT && in getVectorSubVecPointer() 7865 SubVecVT.getVectorNumElements()); in getVectorSubVecPointer()
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| H A D | LegalizeDAG.cpp | 1410 EVT SubVecVT = Part.getValueType(); in ExpandInsertToVectorThroughStack() local 1421 TLI.getVectorSubVecPointer(DAG, StackPtr, VecVT, SubVecVT, Idx); in ExpandInsertToVectorThroughStack()
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| H A D | LegalizeIntegerTypes.cpp | 4766 EVT SubVecVT = SubVec.getValueType(); in PromoteIntRes_INSERT_SUBVECTOR() local 4769 SubVecVT.getVectorElementCount()); in PromoteIntRes_INSERT_SUBVECTOR()
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| H A D | DAGCombiner.cpp | 18440 EVT SubVecVT = SubVec.getValueType(); in combineInsertEltToShuffle() local 18442 unsigned NumSrcElts = SubVecVT.getVectorNumElements(); in combineInsertEltToShuffle() 18447 unsigned ExtendRatio = VT.getSizeInBits() / SubVecVT.getSizeInBits(); in combineInsertEltToShuffle() 18464 EVT SubVecEltVT = SubVecVT.getVectorElementType(); in combineInsertEltToShuffle() 18472 SmallVector<SDValue, 8> ConcatOps(ExtendRatio, DAG.getUNDEF(SubVecVT)); in combineInsertEltToShuffle()
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| /freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 4516 EVT SubVecVT, SDValue Index) const;
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| /freebsd-13.1/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 6182 MVT SubVecVT = SubVec.getSimpleValueType(); in insert1BitVector() local 6183 unsigned SubVecNumElems = SubVecVT.getVectorNumElements(); in insert1BitVector() 6185 IdxVal % SubVecVT.getSizeInBits() == 0 && in insert1BitVector() 6235 Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVecVT, Vec, ZeroIdx); in insert1BitVector() 44804 EVT SubVecVT = SubVec.getValueType(); in combineScalarAndWithMaskSetcc() local 44808 if (SubVec.getOpcode() != ISD::SETCC || !TLI.isTypeLegal(SubVecVT) || in combineScalarAndWithMaskSetcc() 44809 !N->getConstantOperandAPInt(1).isMask(SubVecVT.getVectorNumElements())) in combineScalarAndWithMaskSetcc() 44824 DAG.getConstant(0, dl, SubVecVT)); in combineScalarAndWithMaskSetcc() 50405 MVT SubVecVT = SubVec.getSimpleValueType(); in combineInsertSubvector() local 50438 SubVecVT.getFixedSizeInBits()) in combineInsertSubvector() [all …]
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