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Searched refs:SubRegs (Results 1 – 25 of 33) sorted by relevance

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/freebsd-13.1/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveVariables.cpp195 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastPartialDef() local
219 SubRegs.isValid(); ++SubRegs) in FindLastPartialDef()
249 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandlePhysRegUse() local
273 SubRegs.isValid(); ++SubRegs) in HandlePhysRegUse()
288 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in FindLastRefOrPartRef() local
337 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandlePhysRegKill() local
368 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandlePhysRegKill() local
447 SubRegs.isValid(); ++SubRegs) in HandlePhysRegDef()
450 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandlePhysRegDef() local
472 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandlePhysRegDef() local
[all …]
H A DCriticalAntiDepBreaker.cpp227 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in PrescanInstruction() local
228 SubRegs.isValid(); ++SubRegs) { in PrescanInstruction()
229 KeepRegs.set(*SubRegs); in PrescanInstruction()
239 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in PrescanInstruction() local
240 SubRegs.isValid(); ++SubRegs) in PrescanInstruction()
241 KeepRegs.set(*SubRegs); in PrescanInstruction()
H A DMachineInstrBundle.cpp197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in finalizeBundle() local
198 unsigned SubReg = *SubRegs; in finalizeBundle()
H A DAggressiveAntiDepBreaker.cpp250 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in GetPassthruRegs() local
251 SubRegs.isValid(); ++SubRegs) in GetPassthruRegs()
252 PassthruRegs.insert(*SubRegs); in GetPassthruRegs()
326 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) { in HandleLastUse() local
327 unsigned SubregReg = *SubRegs; in HandleLastUse()
H A DIfConversion.cpp1963 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in IfConvertDiamondCommon() local
1964 SubRegs.isValid(); ++SubRegs) in IfConvertDiamondCommon()
1965 ExtUses.insert(*SubRegs); in IfConvertDiamondCommon()
1971 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in IfConvertDiamondCommon() local
1972 SubRegs.isValid(); ++SubRegs) in IfConvertDiamondCommon()
1973 RedefsByFalse.insert(*SubRegs); in IfConvertDiamondCommon()
H A DBranchFolding.cpp1878 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in findHoistingInsertPosAndDeps() local
1879 Uses.erase(*SubRegs); // Use sub-registers to be conservative in findHoistingInsertPosAndDeps()
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DLivePhysRegs.h82 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); in addReg()
83 SubRegs.isValid(); ++SubRegs) in addReg()
84 LiveRegs.insert(*SubRegs); in addReg()
/freebsd-13.1/contrib/llvm-project/llvm/utils/TableGen/
H A DCodeGenRegisters.cpp254 for (const auto &SubReg : SubRegs) { in inheritRegUnits()
267 return SubRegs; in computeSubRegs()
296 if (!SubRegs.insert(SR).second) in computeSubRegs()
309 CodeGenRegister *SR = SubRegs[Idx]; in computeSubRegs()
354 for (const auto &SubReg : SubRegs) { in computeSubRegs()
445 return SubRegs; in computeSubRegs()
549 for (auto SubReg : SubRegs) in computeSuperRegs()
555 for (auto SubReg : SubRegs) { in computeSuperRegs()
580 for (auto SubReg : SubRegs) in addSubRegsPreOrder()
614 if (Dim != SubRegs->size()) in expand()
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H A DCodeGenRegisters.h185 return SubRegs; in getSubRegs()
278 SubRegMap SubRegs; member
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfo.td42 let SubRegs = [SubReg];
49 let SubRegs = [SubReg];
74 let SubRegs = [SubReg];
82 let SubRegs = [SubReg];
95 let SubRegs = subregs;
106 let SubRegs = subregs;
115 let SubRegs = subregs;
121 let SubRegs = subregs;
128 let SubRegs = [!cast<GP8>("X"#EvenIndex), !cast<GP8>("X"#!add(EvenIndex, 1))];
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/VE/
H A DVERegisterInfo.td19 let SubRegs = subregs;
35 let SubRegs = subregs;
45 let SubRegs = subregs;
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCRegisterInfo.h107 uint32_t SubRegs; // Sub-register set, described above member
291 : mc_difflist_iterator(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs) {} in mc_subreg_iterator()
598 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonCopyToCombine.cpp449 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) in findPotentialNewifiableTFRs() local
450 LastDef[*SubRegs] = &MI; in findPotentialNewifiableTFRs()
H A DHexagonRegisterInfo.td53 let SubRegs = subregs;
74 let SubRegs = subregs;
90 let SubRegs = subregs;
144 let SubRegs = [USR_OVF];
H A DHexagonFrameLowering.cpp251 for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) { in getMax32BitSubRegister() local
253 if (*SubRegs > RegNo) in getMax32BitSubRegister()
254 RegNo = *SubRegs; in getMax32BitSubRegister()
256 if (!RegNo || *SubRegs < RegNo) in getMax32BitSubRegister()
257 RegNo = *SubRegs; in getMax32BitSubRegister()
H A DHexagonInstrInfo.cpp2137 for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs) in isDependent() local
2138 if (RegB == *SubRegs) in isDependent()
2142 for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs) in isDependent() local
2143 if (RegA == *SubRegs) in isDependent()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.td17 let SubRegs = subregs;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYRegisterInfo.td34 let SubRegs = [subreg];
42 let SubRegs = [subreg];
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td36 let SubRegs = subregs;
45 let SubRegs = subregs;
52 let SubRegs = subregs;
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kRegisterInfo.td22 let SubRegs = SUBREGS;
/freebsd-13.1/contrib/llvm-project/llvm/include/llvm/Target/
H A DTarget.td95 // in the SubRegs field of a Register definition. For example:
141 // SubRegs - A list of registers that are parts of this register. Note these
143 // themselves overlap. e.g. For X86, EAX's SubRegs list contains only [AX],
145 list<Register> SubRegs = [];
147 // SubRegIndices - For each register in SubRegs, specify the SubRegIndex used
149 // SubRegs.
194 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
198 let SubRegs = subregs;
376 // SubRegs - N lists of registers to be zipped up. Super-registers are
377 // synthesized from the first element of each SubRegs list, the second
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/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp933 unsigned SubRegs = 0; in copyPhysReg() local
940 SubRegs = 2; in copyPhysReg()
944 SubRegs = 4; in copyPhysReg()
949 SubRegs = 2; in copyPhysReg()
953 SubRegs = 3; in copyPhysReg()
957 SubRegs = 4; in copyPhysReg()
961 SubRegs = 2; in copyPhysReg()
965 SubRegs = 2; in copyPhysReg()
970 SubRegs = 3; in copyPhysReg()
975 SubRegs = 4; in copyPhysReg()
[all …]
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUInstructionSelector.cpp521 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8); in selectG_MERGE_VALUES() local
527 MIB.addImm(SubRegs[I]); in selectG_MERGE_VALUES()
566 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8); in selectG_UNMERGE_VALUES() local
570 .addReg(SrcReg, 0, SubRegs[I]); in selectG_UNMERGE_VALUES()
573 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]); in selectG_UNMERGE_VALUES()
2643 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize); in computeIndirectRegIndex() local
2647 if (static_cast<unsigned>(Offset) >= SubRegs.size()) in computeIndirectRegIndex()
2648 return std::make_pair(IdxReg, SubRegs[0]); in computeIndirectRegIndex()
2649 return std::make_pair(IdxBaseReg, SubRegs[Offset]); in computeIndirectRegIndex()
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td27 let SubRegs = [subreg];
39 let SubRegs = [subreg];
/freebsd-13.1/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp273 const unsigned SubRegs[]);
1227 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1, in createDTuple() local
1230 return createTuple(Regs, RegClassIDs, SubRegs); in createDTuple()
1236 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1, in createQTuple() local
1239 return createTuple(Regs, RegClassIDs, SubRegs); in createQTuple()
1246 static const unsigned SubRegs[] = {AArch64::zsub0, AArch64::zsub1, in createZTuple() local
1249 return createTuple(Regs, RegClassIDs, SubRegs); in createZTuple()
1254 const unsigned SubRegs[]) { in createTuple() argument
1273 Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], DL, MVT::i32)); in createTuple()

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